| /openbmc/linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm-ns.dtsi | 19 ranges = <0x00000000 0x18000000 0x00001000>;
25 reg = <0x0300 0x100>;
33 reg = <0x0400 0x100>;
37 pinctrl-0 = <&pinmux_uart1>;
44 ranges = <0x00000000 0x19000000 0x00023000>;
50 reg = <0x20000 0x100>;
55 reg = <0x20200 0x100>;
62 reg = <0x20600 0x20>;
71 #address-cells = <0>;
73 reg = <0x21000 0x1000>,
[all …]
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| /openbmc/linux/sound/soc/tegra/ |
| H A D | tegra210_adx.c | 25 { TEGRA210_ADX_RX_INT_MASK, 0x00000001},
26 { TEGRA210_ADX_RX_CIF_CTRL, 0x00007000},
27 { TEGRA210_ADX_TX_INT_MASK, 0x0000000f },
28 { TEGRA210_ADX_TX1_CIF_CTRL, 0x00007000},
29 { TEGRA210_ADX_TX2_CIF_CTRL, 0x00007000},
30 { TEGRA210_ADX_TX3_CIF_CTRL, 0x00007000},
31 { TEGRA210_ADX_TX4_CIF_CTRL, 0x00007000},
32 { TEGRA210_ADX_CG, 0x1},
33 { TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000},
45 for (i = 0; i < TEGRA210_ADX_RAM_DEPTH; i++) in tegra210_adx_write_map_ram()
[all …]
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| H A D | tegra210_amx.c | 34 #define TEGRA194_MAX_FRAME_IDLE_COUNT 0x1800
39 { TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
40 { TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},
41 { TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},
42 { TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},
43 { TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},
44 { TEGRA210_AMX_TX_INT_MASK, 0x00000001},
45 { TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},
46 { TEGRA210_AMX_CG, 0x1},
47 { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},
[all …]
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| /openbmc/linux/arch/sparc/include/uapi/asm/ |
| H A D | perfctr.h | 58 #define PRIV 0x00000001
59 #define SYS 0x00000002
60 #define USR 0x00000004
63 #define CYCLE_CNT 0x00000000
64 #define INSTR_CNT 0x00000010
65 #define DISPATCH0_IC_MISS 0x00000020
66 #define DISPATCH0_STOREBUF 0x00000030
67 #define IC_REF 0x00000080
68 #define DC_RD 0x00000090
69 #define DC_WR 0x000000A0
[all …]
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| /openbmc/linux/include/linux/bcma/ |
| H A D | bcma_driver_arm_c9.h | 6 #define BCMA_DMU_CRU_USB2_CONTROL 0x0164
7 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK 0x00000FFC
9 #define BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK 0x00007000
11 #define BCMA_DMU_CRU_CLKSET_KEY 0x0180
12 #define BCMA_DMU_CRU_STRAPS_CTRL 0x02A0
13 #define BCMA_DMU_CRU_STRAPS_CTRL_USB3 0x00000010
14 #define BCMA_DMU_CRU_STRAPS_CTRL_4BYTE 0x00008000
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | smc.h | 16 #define DRP 0x00
17 #define DTR0 0x01
18 #define DTR1 0x02
19 #define DTR2 0x03
20 #define DTR3 0x04
21 #define DTR4 0x05
22 #define DPMC0 0x06
23 #define DPMC1 0x07
24 #define DRFC 0x08
25 #define DSCH 0x09
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | mc_cgm_regs.h | 13 #define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) )
14 #define MC_CGM_SC_SEL_FIRC (0x0)
15 #define MC_CGM_SC_SEL_XOSC (0x1)
16 #define MC_CGM_SC_SEL_ARMPLL (0x2)
17 #define MC_CGM_SC_SEL_CLKDISABLE (0xF)
20 #define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
22 #define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000)
25 #define MC_CGM_SC_SEL_MASK (0x0F000000)
29 #define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
41 #define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000)
[all …]
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| /openbmc/qemu/hw/usb/ |
| H A D | hcd-ehci.h | 28 #define EHCI_DEBUG 0
37 #define MMIO_SIZE 0x1000
38 #define CAPA_SIZE 0x10
56 #define ITD_XACT_LENGTH_MASK 0x0fff0000
59 #define ITD_XACT_PGSEL_MASK 0x00007000
61 #define ITD_XACT_OFFSET_MASK 0x00000fff
64 #define ITD_BUFPTR_MASK 0xfffff000
66 #define ITD_BUFPTR_EP_MASK 0x00000f00
68 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
69 #define ITD_BUFPTR_DEVADDR_SH 0
[all …]
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| /openbmc/linux/include/uapi/linux/ |
| H A D | vbox_vmmdev_types.h | 24 VMMDEVREQ_INVALID_REQUEST = 0,
39 VMMDEVREQ_REPORT_GUEST_INFO2 = 58, /* since version 3.2.0 */
64 VMMDEVREQ_VIDEMODE_SUPPORTED2 = 57, /* since version 3.2.0 */
99 VMMDEVREQ_SIZEHACK = 0x7fffffff
111 #define VMMDEV_REQUESTOR_USR_NOT_GIVEN 0x00000000
113 #define VMMDEV_REQUESTOR_USR_DRV 0x00000001
115 #define VMMDEV_REQUESTOR_USR_DRV_OTHER 0x00000002
117 #define VMMDEV_REQUESTOR_USR_ROOT 0x00000003
119 #define VMMDEV_REQUESTOR_USR_USER 0x00000006
121 #define VMMDEV_REQUESTOR_USR_MASK 0x00000007
[all …]
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| /openbmc/u-boot/include/ |
| H A D | lcdvideo.h | 11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
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| /openbmc/linux/drivers/media/pci/cx88/ |
| H A D | cx88-tvaudio.c | 52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | gm200.c | 29 nvkm_falcon_wr32(falcon, 0x200, 0x0000030e); in gm200_pmu_flcn_bind_stat()
30 return (nvkm_falcon_rd32(falcon, 0x20c) & 0x00007000) >> 12; in gm200_pmu_flcn_bind_stat()
36 nvkm_falcon_wr32(falcon, 0xe00, 4); /* DMAIDX_UCODE */ in gm200_pmu_flcn_bind_inst()
37 nvkm_falcon_wr32(falcon, 0xe04, 0); /* DMAIDX_VIRT */ in gm200_pmu_flcn_bind_inst()
38 nvkm_falcon_wr32(falcon, 0xe08, 4); /* DMAIDX_PHYS_VID */ in gm200_pmu_flcn_bind_inst()
39 nvkm_falcon_wr32(falcon, 0xe0c, 5); /* DMAIDX_PHYS_SYS_COH */ in gm200_pmu_flcn_bind_inst()
40 nvkm_falcon_wr32(falcon, 0xe10, 6); /* DMAIDX_PHYS_SYS_NCOH */ in gm200_pmu_flcn_bind_inst()
41 nvkm_falcon_mask(falcon, 0x090, 0x00010000, 0x00010000); in gm200_pmu_flcn_bind_inst()
42 nvkm_falcon_wr32(falcon, 0x480, (1 << 30) | (target << 28) | (addr >> 12)); in gm200_pmu_flcn_bind_inst()
51 .debug = 0xc08,
[all …]
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| /openbmc/linux/drivers/gpu/drm/mcde/ |
| H A D | mcde_drm.h | 13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
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| /openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | nvidia,tegra-ahci.yaml | 67 - const: sata-0
164 reg = <0x70027000 0x00002000>, /* AHCI */
165 <0x70020000 0x00007000>, /* SATA */
166 <0x70001100 0x00010000>; /* SATA AUX */
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| /openbmc/linux/drivers/net/ethernet/intel/iavf/ |
| H A D | iavf_register.h | 7 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
8 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
9 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
10 #define IAVF_VF_ARQH1_ARQH_SHIFT 0
11 #define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
12 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
14 #define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
16 #define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
18 #define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
20 #define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
[all …]
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| /openbmc/linux/arch/arm/nwfpe/ |
| H A D | fpsr.h | 32 #define MASK_SYSID 0xff000000
33 #define BIT_HARDWARE 0x80000000
34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
40 #define MASK_TRAP_ENABLE 0x00ff0000
41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
42 #define BIT_IXE 0x00100000 /* inexact exception enable */
43 #define BIT_UFE 0x00080000 /* underflow exception enable */
44 #define BIT_OFE 0x00040000 /* overflow exception enable */
45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
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| /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | serdes.c | 19 #define FSL_SRDSCR0_OFFS 0x0
20 #define FSL_SRDSCR0_DPP_1V2 0x00008800
21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
24 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
25 #define FSL_SRDSCR1_OFFS 0x4
26 #define FSL_SRDSCR1_PLLBW 0x00000040
27 #define FSL_SRDSCR2_OFFS 0x8
28 #define FSL_SRDSCR2_VDD_1V2 0x00800000
[all …]
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | fsl_rio.h | 32 #define RIO_MAINT_WIN_SIZE 0x400000
33 #define RIO_LTLEDCSR 0x0608
35 #define DOORBELL_ROWAR_EN 0x80000000
36 #define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
37 #define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
38 #define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
39 #define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
40 #define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserved */
41 #define DOORBELL_ROWAR_MAINTWD 0x00007000
42 #define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
[all …]
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| /openbmc/linux/sound/soc/qcom/qdsp6/ |
| H A D | audioreach.h | 12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
14 #define MODULE_ID_GAIN 0x07001002
15 #define MODULE_ID_PCM_CNV 0x07001003
16 #define MODULE_ID_PCM_ENC 0x07001004
17 #define MODULE_ID_PCM_DEC 0x07001005
18 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008
19 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009
20 #define MODULE_ID_SAL 0x07001010
21 #define MODULE_ID_MFC 0x07001015
[all …]
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| /openbmc/qemu/linux-user/arm/nwfpe/ |
| H A D | fpsr.h | 43 #define MASK_SYSID 0xff000000
44 #define BIT_HARDWARE 0x80000000
45 #define FP_EMULATOR 0x01000000 /* System ID for emulator */
46 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
51 #define MASK_TRAP_ENABLE 0x00ff0000
52 #define MASK_TRAP_ENABLE_STRICT 0x001f0000
53 #define BIT_IXE 0x00100000 /* inexact exception enable */
54 #define BIT_UFE 0x00080000 /* underflow exception enable */
55 #define BIT_OFE 0x00040000 /* overflow exception enable */
56 #define BIT_DZE 0x00020000 /* divide by zero exception enable */
[all …]
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| /openbmc/linux/include/soc/fsl/qe/ |
| H A D | qe.h | 32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
227 return 0; in qe_alive_during_sleep()
271 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
284 __be32 traps[16]; /* Trap addresses, 0 == ignore */
328 #define BD_STATUS_MASK 0xffff0000
329 #define BD_LENGTH_MASK 0x0000ffff
337 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
338 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
339 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | dcr-regs.h | 29 #define DCRN_CPR0_CONFIG_ADDR 0xc
30 #define DCRN_CPR0_CONFIG_DATA 0xd
33 #define DCRN_SDR0_CONFIG_ADDR 0xe
34 #define DCRN_SDR0_CONFIG_DATA 0xf
36 #define SDR0_PFC0 0x4100
37 #define SDR0_PFC1 0x4101
38 #define SDR0_PFC1_EPS 0x1c00000
40 #define SDR0_PFC1_RMII 0x02000000
41 #define SDR0_MFR 0x4300
42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
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| H A D | 8xx_immap.h | 29 char res2[0xc];
31 char res3[0x4c];
53 char res1[0x20];
83 char res1[0x24];
92 char res3[0x80];
98 #define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99 #define BR_AT_MSK 0x00007000 /* Address Type Mask */
100 #define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101 #define BR_PS_32 0x00000000 /* 32 bit port size */
102 #define BR_PS_16 0x00000800 /* 16 bit port size */
[all …]
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| /openbmc/linux/arch/arm/boot/dts/sigmastar/ |
| H A D | mstar-v7.dtsi | 18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]
|