| /openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/ |
| H A D | southcluster.asl | 11 Name(_ADR, 0)
12 Name(_BBN, 0)
18 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
20 /* IO Region 0 */
22 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
25 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
29 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
31 /* VGA memory (0xa0000-0xbffff) */
34 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
35 0x00020000, , , ASEG)
[all …]
|
| /openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| H A D | southcluster.asl | 14 Name(_ADR, 0)
15 Name(_BBN, 0)
21 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
23 /* IO Region 0 */
25 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
28 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
32 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
34 /* VGA memory (0xa0000-0xbffff) */
37 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
38 0x00020000, , , ASEG)
[all …]
|
| /openbmc/linux/drivers/gpu/drm/etnaviv/ |
| H A D | common.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | loongson.yaml | 56 reg = <0x0 0x1a000000 0x0 0x2000000>;
59 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
60 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
|
| /openbmc/u-boot/board/terasic/de10-nano/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
|
| /openbmc/u-boot/board/terasic/de0-nano-soc/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
|
| /openbmc/u-boot/board/is1/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/u-boot/board/sr1500/qts/ |
| H A D | iocsr_config.h | 15 0x00100000,
16 0x40000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x000E0180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/u-boot/drivers/mmc/ |
| H A D | arm_pl180_mmci.h | 22 #define INIT_PWR 0xBF /* Power on, full power, not open drain */
26 #define SDI_PWR_PWRCTRL_MASK 0x00000003
27 #define SDI_PWR_PWRCTRL_ON 0x00000003
28 #define SDI_PWR_PWRCTRL_OFF 0x00000000
29 #define SDI_PWR_DAT2DIREN 0x00000004
30 #define SDI_PWR_CMDDIREN 0x00000008
31 #define SDI_PWR_DAT0DIREN 0x00000010
32 #define SDI_PWR_DAT31DIREN 0x00000020
33 #define SDI_PWR_OPD 0x00000040
34 #define SDI_PWR_FBCLKEN 0x00000080
[all …]
|
| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | m5272.h | 20 #define GPIO_PACNT_PA15MSK (0xC0000000)
21 #define GPIO_PACNT_DGNT1 (0x40000000)
22 #define GPIO_PACNT_PA14MSK (0x30000000)
23 #define GPIO_PACNT_DREQ1 (0x10000000)
24 #define GPIO_PACNT_PA13MSK (0x0C000000)
25 #define GPIO_PACNT_DFSC3 (0x04000000)
26 #define GPIO_PACNT_PA12MSK (0x03000000)
27 #define GPIO_PACNT_DFSC2 (0x01000000)
28 #define GPIO_PACNT_PA11MSK (0x00C00000)
29 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
|
| /openbmc/u-boot/board/samtec/vining_fpga/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/u-boot/board/devboards/dbm-soc1/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00004824,
22 0x01209000,
23 0x82400000,
24 0x00018004,
[all …]
|
| /openbmc/u-boot/board/terasic/sockit/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/u-boot/board/ebv/socrates/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00004824,
22 0x01209000,
23 0x82400000,
24 0x00018004,
[all …]
|
| /openbmc/u-boot/board/terasic/de1-soc/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/linux/arch/mips/include/asm/sgi/ |
| H A D | mc.h | 18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
19 #define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
20 #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
21 #define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
23 #define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
24 #define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
25 #define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
26 #define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
27 #define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
[all …]
|
| /openbmc/linux/drivers/net/usb/ |
| H A D | smsc75xx.h | 12 #define TX_CMD_A_LSO (0x08000000)
13 #define TX_CMD_A_IPE (0x04000000)
14 #define TX_CMD_A_TPE (0x02000000)
15 #define TX_CMD_A_IVTG (0x01000000)
16 #define TX_CMD_A_RVTG (0x00800000)
17 #define TX_CMD_A_FCS (0x00400000)
18 #define TX_CMD_A_LEN (0x000FFFFF)
20 #define TX_CMD_B_MSS (0x3FFF0000)
23 #define TX_CMD_B_VTAG (0x0000FFFF)
26 #define RX_CMD_A_ICE (0x80000000)
[all …]
|
| H A D | lan78xx.h | 9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_0_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_0_default.h | 26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
|
| /openbmc/u-boot/drivers/ata/ |
| H A D | dwc_ahsata_priv.h | 22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-spear/ |
| H A D | spr_misc.h | 11 u32 auto_cfg_reg; /* 0x0 */
12 u32 armdbg_ctr_reg; /* 0x4 */
13 u32 pll1_cntl; /* 0x8 */
14 u32 pll1_frq; /* 0xc */
15 u32 pll1_mod; /* 0x10 */
16 u32 pll2_cntl; /* 0x14 */
17 u32 pll2_frq; /* 0x18 */
18 u32 pll2_mod; /* 0x1C */
19 u32 pll_ctr_reg; /* 0x20 */
20 u32 amba_clk_cfg; /* 0x24 */
[all …]
|
| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap4460.dtsi | 12 cpu0: cpu@0 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
39 #thermal-sensor-cells = <0>;
45 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
46 <0x4A002268 0x4>;
52 1025000 0 0 0 0 0
53 1200000 0 0 0 0 0
[all …]
|
| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | keylargo.h | 10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
|
| /openbmc/linux/drivers/net/ethernet/renesas/ |
| H A D | ravb.h | 38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
|