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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h12 #define DPCD_RC00_DPCD_REV 0x00000
13 #define DPCD_RC01_MAX_LINK_RATE 0x00001
14 #define DPCD_RC02 0x00002
15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
16 #define DPCD_RC02_TPS3_SUPPORTED 0x40
17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f
18 #define DPCD_RC03 0x00003
19 #define DPCD_RC03_TPS4_SUPPORTED 0x80
20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01
21 #define DPCD_RC0E 0x0000e
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/openbmc/linux/include/uapi/linux/
H A Dmedia.h48 #define MEDIA_ENT_F_BASE 0x00000000
49 #define MEDIA_ENT_F_OLD_BASE 0x00010000
50 #define MEDIA_ENT_F_OLD_SUBDEV_BASE 0x00020000
68 #define MEDIA_ENT_F_DTV_DEMOD (MEDIA_ENT_F_BASE + 0x00001)
69 #define MEDIA_ENT_F_TS_DEMUX (MEDIA_ENT_F_BASE + 0x00002)
70 #define MEDIA_ENT_F_DTV_CA (MEDIA_ENT_F_BASE + 0x00003)
71 #define MEDIA_ENT_F_DTV_NET_DECAP (MEDIA_ENT_F_BASE + 0x00004)
77 #define MEDIA_ENT_F_IO_DTV (MEDIA_ENT_F_BASE + 0x01001)
78 #define MEDIA_ENT_F_IO_VBI (MEDIA_ENT_F_BASE + 0x01002)
79 #define MEDIA_ENT_F_IO_SWRADIO (MEDIA_ENT_F_BASE + 0x01003)
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_audmix.c38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
53 { .tdms = 0, .clk = 0, .msg = "" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
73 { .tdms = 0, .clk = 0, .msg = "" },
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
[all …]
/openbmc/linux/drivers/clk/mmp/
H A Dclk-of-mmp2.c25 #define APBC_RTC 0x0
26 #define APBC_TWSI0 0x4
27 #define APBC_TWSI1 0x8
28 #define APBC_TWSI2 0xc
29 #define APBC_TWSI3 0x10
30 #define APBC_TWSI4 0x7c
31 #define APBC_TWSI5 0x80
32 #define APBC_KPC 0x18
33 #define APBC_TIMER 0x24
34 #define APBC_UART0 0x2c
[all …]
/openbmc/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h34 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
41 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
42 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
48 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
[all …]
/openbmc/qemu/target/mips/
H A Dcpu.h42 # define FP_ENDIAN_IDX 0
63 #define FCR0_REV 0
73 } while (0)
77 } while (0)
78 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
79 (((env).fcr31 >> 23) & 0x1))
80 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
81 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
82 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
83 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
[all …]
/openbmc/linux/drivers/perf/hisilicon/
H A Dhns3_pmu.c29 #define HNS3_PMU_REG_GLOBAL_CTRL 0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ 0x0020
31 #define HNS3_PMU_REG_BDF 0x0fe0
32 #define HNS3_PMU_REG_VERSION 0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID 0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET 0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE 0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW 0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH 0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS 0x08
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dsuni1x10gexp_regs.h29 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
37 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
44 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
57 #define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
58 #define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
59 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
60 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
61 #define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
62 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
64 #define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
[all …]