1*a6013785SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2f7917c00SJeff Kirsher /***************************************************************************** 3f7917c00SJeff Kirsher * * 4f7917c00SJeff Kirsher * File: suni1x10gexp_regs.h * 5f7917c00SJeff Kirsher * $Revision: 1.9 $ * 6f7917c00SJeff Kirsher * $Date: 2005/06/22 00:17:04 $ * 7f7917c00SJeff Kirsher * Description: * 8f7917c00SJeff Kirsher * PMC/SIERRA (pm3393) MAC-PHY functionality. * 9f7917c00SJeff Kirsher * part of the Chelsio 10Gb Ethernet Driver. * 10f7917c00SJeff Kirsher * * 11f7917c00SJeff Kirsher * * 12f7917c00SJeff Kirsher * http://www.chelsio.com * 13f7917c00SJeff Kirsher * * 14f7917c00SJeff Kirsher * Maintainers: maintainers@chelsio.com * 15f7917c00SJeff Kirsher * * 16f7917c00SJeff Kirsher * Authors: PMC/SIERRA * 17f7917c00SJeff Kirsher * * 18f7917c00SJeff Kirsher * History: * 19f7917c00SJeff Kirsher * * 20f7917c00SJeff Kirsher ****************************************************************************/ 21f7917c00SJeff Kirsher 22f7917c00SJeff Kirsher #ifndef _CXGB_SUNI1x10GEXP_REGS_H_ 23f7917c00SJeff Kirsher #define _CXGB_SUNI1x10GEXP_REGS_H_ 24f7917c00SJeff Kirsher 25f7917c00SJeff Kirsher /* 26f7917c00SJeff Kirsher ** Space allocated for each Exact Match Filter 27f7917c00SJeff Kirsher ** There are 8 filter configurations 28f7917c00SJeff Kirsher */ 29f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003 30f7917c00SJeff Kirsher 31f7917c00SJeff Kirsher #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER ) 32f7917c00SJeff Kirsher 33f7917c00SJeff Kirsher /* 34f7917c00SJeff Kirsher ** Space allocated for VLAN-Id Filter 35f7917c00SJeff Kirsher ** There are 8 filter configurations 36f7917c00SJeff Kirsher */ 37f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001 38f7917c00SJeff Kirsher 39f7917c00SJeff Kirsher #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER ) 40f7917c00SJeff Kirsher 41f7917c00SJeff Kirsher /* 42f7917c00SJeff Kirsher ** Space allocated for each MSTAT Counter 43f7917c00SJeff Kirsher */ 44f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004 45f7917c00SJeff Kirsher 46f7917c00SJeff Kirsher #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT ) 47f7917c00SJeff Kirsher 48f7917c00SJeff Kirsher 49f7917c00SJeff Kirsher /******************************************************************************/ 50f7917c00SJeff Kirsher /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ 51f7917c00SJeff Kirsher /******************************************************************************/ 52f7917c00SJeff Kirsher /* Refer to the Register Bit Masks bellow for the naming of each register and */ 53f7917c00SJeff Kirsher /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ 54f7917c00SJeff Kirsher /******************************************************************************/ 55f7917c00SJeff Kirsher 56f7917c00SJeff Kirsher 57f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000 58f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001 59f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002 60f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003 61f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004 62f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005 63f7917c00SJeff Kirsher 64f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006 65f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007 66f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008 67f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009 68f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A 69f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B 70f7917c00SJeff Kirsher 71f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C 72f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D 73f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E 74f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_FREE 0x000F 75f7917c00SJeff Kirsher 76f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010 77f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011 78f7917c00SJeff Kirsher 79f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100 80f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101 81f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102 82f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103 83f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104 84f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107 85f7917c00SJeff Kirsher 86f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040 87f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041 88f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042 89f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043 90f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045 91f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046 92f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047 93f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048 94f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049 95f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 96f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 97f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 98f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)) 99f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A 100f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B 101f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C 102f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D 103f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E 104f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F 105f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050 106f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051 107f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052 108f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053 109f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054 110f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055 111f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056 112f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057 113f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058 114f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059 115f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A 116f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B 117f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C 118f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D 119f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E 120f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F 121f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060 122f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061 123f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062 124f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063 125f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064 126f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065 127f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066 128f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067 129f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068 130f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069 131f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A 132f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B 133f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C 134f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D 135f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E 136f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F 137f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070 138f7917c00SJeff Kirsher 139f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081 140f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084 141f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085 142f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086 143f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087 144f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088 145f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089 146f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A 147f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B 148f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C 149f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092 150f7917c00SJeff Kirsher 151f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0 152f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1 153f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2 154f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3 155f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4 156f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5 157f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7 158f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8 159f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9 160f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA 161f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB 162f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC 163f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD 164f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE 165f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF 166f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0 167f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1 168f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2 169f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3 170f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4 171f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5 172f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6 173f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7 174f7917c00SJeff Kirsher 175f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 176f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101 177f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102 178f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103 179f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104 180f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105 181f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106 182f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107 183f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108 184f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109 185f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A 186f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B 187f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C 188f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 189f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 190f7917c00SJeff Kirsher #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 191f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110 192f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111 193f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112 194f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113 195f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114 196f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115 197f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116 198f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117 199f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118 200f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119 201f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A 202f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B 203f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C 204f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D 205f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E 206f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F 207f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120 208f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121 209f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122 210f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123 211f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124 212f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125 213f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126 214f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127 215f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128 216f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129 217f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A 218f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B 219f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C 220f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D 221f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E 222f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F 223f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130 224f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131 225f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132 226f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133 227f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134 228f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135 229f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136 230f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137 231f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138 232f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139 233f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A 234f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B 235f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C 236f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D 237f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E 238f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F 239f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140 240f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141 241f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142 242f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143 243f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144 244f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145 245f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146 246f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147 247f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148 248f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149 249f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A 250f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B 251f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C 252f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D 253f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E 254f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F 255f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150 256f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151 257f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152 258f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153 259f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154 260f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155 261f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156 262f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157 263f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158 264f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159 265f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A 266f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B 267f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C 268f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D 269f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E 270f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F 271f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160 272f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161 273f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162 274f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163 275f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164 276f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165 277f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166 278f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167 279f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168 280f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169 281f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A 282f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B 283f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C 284f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D 285f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E 286f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F 287f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170 288f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171 289f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172 290f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173 291f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174 292f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175 293f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176 294f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177 295f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178 296f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179 297f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a 298f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b 299f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c 300f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d 301f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e 302f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f 303f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180 304f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181 305f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182 306f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183 307f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184 308f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185 309f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186 310f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187 311f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188 312f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189 313f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A 314f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B 315f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C 316f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D 317f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E 318f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F 319f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190 320f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191 321f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192 322f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193 323f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194 324f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195 325f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196 326f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197 327f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198 328f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199 329f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A 330f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B 331f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C 332f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D 333f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E 334f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F 335f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0 336f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1 337f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2 338f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3 339f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4 340f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5 341f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6 342f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7 343f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8 344f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9 345f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA 346f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB 347f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC 348f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD 349f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE 350f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF 351f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0 352f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1 353f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2 354f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3 355f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4 356f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5 357f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6 358f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7 359f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8 360f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9 361f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA 362f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB 363f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC 364f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD 365f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE 366f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF 367f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0 368f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1 369f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2 370f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3 371f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4 372f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5 373f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6 374f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7 375f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8 376f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9 377f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA 378f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB 379f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC 380f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD 381f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE 382f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF 383f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0 384f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1 385f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2 386f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3 387f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4 388f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5 389f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6 390f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7 391f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8 392f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9 393f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA 394f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB 395f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC 396f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD 397f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE 398f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF 399f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0 400f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1 401f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2 402f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3 403f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4 404f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5 405f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6 406f7917c00SJeff Kirsher #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51 407f7917c00SJeff Kirsher 408f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200 409f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201 410f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209 411f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A 412f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D 413f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E 414f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F 415f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210 416f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211 417f7917c00SJeff Kirsher 418f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240 419f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241 420f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242 421f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243 422f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244 423f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245 424f7917c00SJeff Kirsher 425f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280 426f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282 427f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283 428f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284 429f7917c00SJeff Kirsher 430f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300 431f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301 432f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302 433f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303 434f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304 435f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305 436f7917c00SJeff Kirsher 437f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040 438f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041 439f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042 440f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043 441f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044 442f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045 443f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046 444f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047 445f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048 446f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049 447f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D 448f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E 449f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051 450f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052 451f7917c00SJeff Kirsher 452f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080 453f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084 454f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085 455f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086 456f7917c00SJeff Kirsher 457f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0 458f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1 459f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2 460f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3 461f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4 462f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5 463f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6 464f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7 465f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8 466f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9 467f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA 468f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB 469f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC 470f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD 471f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE 472f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF 473f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0 474f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1 475f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2 476f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3 477f7917c00SJeff Kirsher 478f7917c00SJeff Kirsher 479f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200 480f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201 481f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202 482f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203 483f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204 484f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205 485f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206 486f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207 487f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C 488f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D 489f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210 490f7917c00SJeff Kirsher 491f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280 492f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282 493f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283 494f7917c00SJeff Kirsher 495f7917c00SJeff Kirsher 496f7917c00SJeff Kirsher /*----------------------------------------*/ 497f7917c00SJeff Kirsher #define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480 498f7917c00SJeff Kirsher 499f7917c00SJeff Kirsher /******************************************************************************/ 500f7917c00SJeff Kirsher /* -- End register offset definitions -- */ 501f7917c00SJeff Kirsher /******************************************************************************/ 502f7917c00SJeff Kirsher 503f7917c00SJeff Kirsher /******************************************************************************/ 504f7917c00SJeff Kirsher /** SUNI-1x10GE-XP REGISTER BIT MASKS **/ 505f7917c00SJeff Kirsher /******************************************************************************/ 506f7917c00SJeff Kirsher 507f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_1 0x00001 508f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_2 0x00003 509f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_3 0x00007 510f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f 511f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f 512f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f 513f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f 514f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff 515f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff 516f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff 517f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff 518f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff 519f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff 520f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff 521f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff 522f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff 523f7917c00SJeff Kirsher 524f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15) 525f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14) 526f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13) 527f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12) 528f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11) 529f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10) 530f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9) 531f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8) 532f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7) 533f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6) 534f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5) 535f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4) 536f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3) 537f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2) 538f7917c00SJeff Kirsher #define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1) 539f7917c00SJeff Kirsher 540f7917c00SJeff Kirsher #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0) 541f7917c00SJeff Kirsher 542f7917c00SJeff Kirsher 543f7917c00SJeff Kirsher 544f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 545f7917c00SJeff Kirsher * Register 0x0001: S/UNI-1x10GE-XP Product Revision 546f7917c00SJeff Kirsher * Bit 3-0 REVISION 547f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 548f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_REVISION 0x000F 549f7917c00SJeff Kirsher 550f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 551f7917c00SJeff Kirsher * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control 552f7917c00SJeff Kirsher * Bit 2 XAUI_ARESETB 553f7917c00SJeff Kirsher * Bit 1 PL4_ARESETB 554f7917c00SJeff Kirsher * Bit 0 DRESETB 555f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 556f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004 557f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002 558f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_DRESETB 0x0001 559f7917c00SJeff Kirsher 560f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 561f7917c00SJeff Kirsher * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control 562f7917c00SJeff Kirsher * Bit 11 PL4IO_OUTCLKSEL 563f7917c00SJeff Kirsher * Bit 9 SYSPCSLB 564f7917c00SJeff Kirsher * Bit 8 LINEPCSLB 565f7917c00SJeff Kirsher * Bit 7 MSTAT_BYPASS 566f7917c00SJeff Kirsher * Bit 6 RXXG_BYPASS 567f7917c00SJeff Kirsher * Bit 5 TXXG_BYPASS 568f7917c00SJeff Kirsher * Bit 4 SOP_PAD_EN 569f7917c00SJeff Kirsher * Bit 1 LOS_INV 570f7917c00SJeff Kirsher * Bit 0 OVERRIDE_LOS 571f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 572f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800 573f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200 574f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100 575f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080 576f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040 577f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020 578f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010 579f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002 580f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001 581f7917c00SJeff Kirsher 582f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 583f7917c00SJeff Kirsher * Register 0x0004: S/UNI-1x10GE-XP Device Status 584f7917c00SJeff Kirsher * Bit 9 TOP_SXRA_EXPIRED 585f7917c00SJeff Kirsher * Bit 8 TOP_MDIO_BUSY 586f7917c00SJeff Kirsher * Bit 7 TOP_DTRB 587f7917c00SJeff Kirsher * Bit 6 TOP_EXPIRED 588f7917c00SJeff Kirsher * Bit 5 TOP_PAUSED 589f7917c00SJeff Kirsher * Bit 4 TOP_PL4_ID_DOOL 590f7917c00SJeff Kirsher * Bit 3 TOP_PL4_IS_DOOL 591f7917c00SJeff Kirsher * Bit 2 TOP_PL4_ID_ROOL 592f7917c00SJeff Kirsher * Bit 1 TOP_PL4_IS_ROOL 593f7917c00SJeff Kirsher * Bit 0 TOP_PL4_OUT_ROOL 594f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 595f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200 596f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100 597f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080 598f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040 599f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020 600f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010 601f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008 602f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004 603f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002 604f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001 605f7917c00SJeff Kirsher 606f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 607f7917c00SJeff Kirsher * Register 0x0005: Global Performance Update and Clock Monitors 608f7917c00SJeff Kirsher * Bit 15 TIP 609f7917c00SJeff Kirsher * Bit 8 XAUI_REF_CLKA 610f7917c00SJeff Kirsher * Bit 7 RXLANE3CLKA 611f7917c00SJeff Kirsher * Bit 6 RXLANE2CLKA 612f7917c00SJeff Kirsher * Bit 5 RXLANE1CLKA 613f7917c00SJeff Kirsher * Bit 4 RXLANE0CLKA 614f7917c00SJeff Kirsher * Bit 3 CSUCLKA 615f7917c00SJeff Kirsher * Bit 2 TDCLKA 616f7917c00SJeff Kirsher * Bit 1 RSCLKA 617f7917c00SJeff Kirsher * Bit 0 RDCLKA 618f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 619f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TIP 0x8000 620f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100 621f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080 622f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040 623f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020 624f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010 625f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008 626f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004 627f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002 628f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001 629f7917c00SJeff Kirsher 630f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 631f7917c00SJeff Kirsher * Register 0x0006: MDIO Command 632f7917c00SJeff Kirsher * Bit 4 MDIO_RDINC 633f7917c00SJeff Kirsher * Bit 3 MDIO_RSTAT 634f7917c00SJeff Kirsher * Bit 2 MDIO_LCTLD 635f7917c00SJeff Kirsher * Bit 1 MDIO_LCTLA 636f7917c00SJeff Kirsher * Bit 0 MDIO_SPRE 637f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 638f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010 639f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008 640f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004 641f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002 642f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001 643f7917c00SJeff Kirsher 644f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 645f7917c00SJeff Kirsher * Register 0x0007: MDIO Interrupt Enable 646f7917c00SJeff Kirsher * Bit 0 MDIO_BUSY_EN 647f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 648f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001 649f7917c00SJeff Kirsher 650f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 651f7917c00SJeff Kirsher * Register 0x0008: MDIO Interrupt Status 652f7917c00SJeff Kirsher * Bit 0 MDIO_BUSYI 653f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 654f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001 655f7917c00SJeff Kirsher 656f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 657f7917c00SJeff Kirsher * Register 0x0009: MMD PHY Address 658f7917c00SJeff Kirsher * Bit 12-8 MDIO_DEVADR 659f7917c00SJeff Kirsher * Bit 4-0 MDIO_PRTADR 660f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 661f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00 662f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8 663f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F 664f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0 665f7917c00SJeff Kirsher 666f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 667f7917c00SJeff Kirsher * Register 0x000C: OAM Interface Control 668f7917c00SJeff Kirsher * Bit 6 MDO_OD_ENB 669f7917c00SJeff Kirsher * Bit 5 MDI_INV 670f7917c00SJeff Kirsher * Bit 4 MDI_SEL 671f7917c00SJeff Kirsher * Bit 3 RXOAMEN 672f7917c00SJeff Kirsher * Bit 2 RXOAMCLKEN 673f7917c00SJeff Kirsher * Bit 1 TXOAMEN 674f7917c00SJeff Kirsher * Bit 0 TXOAMCLKEN 675f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 676f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040 677f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020 678f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010 679f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008 680f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004 681f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002 682f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001 683f7917c00SJeff Kirsher 684f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 685f7917c00SJeff Kirsher * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status 686f7917c00SJeff Kirsher * Bit 15 TOP_PL4IO_INT 687f7917c00SJeff Kirsher * Bit 14 TOP_IRAM_INT 688f7917c00SJeff Kirsher * Bit 13 TOP_ERAM_INT 689f7917c00SJeff Kirsher * Bit 12 TOP_XAUI_INT 690f7917c00SJeff Kirsher * Bit 11 TOP_MSTAT_INT 691f7917c00SJeff Kirsher * Bit 10 TOP_RXXG_INT 692f7917c00SJeff Kirsher * Bit 9 TOP_TXXG_INT 693f7917c00SJeff Kirsher * Bit 8 TOP_XRF_INT 694f7917c00SJeff Kirsher * Bit 7 TOP_XTEF_INT 695f7917c00SJeff Kirsher * Bit 6 TOP_MDIO_BUSY_INT 696f7917c00SJeff Kirsher * Bit 5 TOP_RXOAM_INT 697f7917c00SJeff Kirsher * Bit 4 TOP_TXOAM_INT 698f7917c00SJeff Kirsher * Bit 3 TOP_IFLX_INT 699f7917c00SJeff Kirsher * Bit 2 TOP_EFLX_INT 700f7917c00SJeff Kirsher * Bit 1 TOP_PL4ODP_INT 701f7917c00SJeff Kirsher * Bit 0 TOP_PL4IDU_INT 702f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 703f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000 704f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000 705f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000 706f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000 707f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800 708f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400 709f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200 710f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100 711f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080 712f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040 713f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020 714f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010 715f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008 716f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004 717f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002 718f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001 719f7917c00SJeff Kirsher 720f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 721f7917c00SJeff Kirsher * Register 0x000E:PM3393 Global interrupt enable 722f7917c00SJeff Kirsher * Bit 15 TOP_INTE 723f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 724f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000 725f7917c00SJeff Kirsher 726f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 727f7917c00SJeff Kirsher * Register 0x0010: XTEF Miscellaneous Control 728f7917c00SJeff Kirsher * Bit 7 RF_VAL 729f7917c00SJeff Kirsher * Bit 6 RF_OVERRIDE 730f7917c00SJeff Kirsher * Bit 5 LF_VAL 731f7917c00SJeff Kirsher * Bit 4 LF_OVERRIDE 732f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 733f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080 734f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040 735f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020 736f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010 737f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0 738f7917c00SJeff Kirsher 739f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 740f7917c00SJeff Kirsher * Register 0x0011: XRF Miscellaneous Control 741f7917c00SJeff Kirsher * Bit 6-4 EN_IDLE_REP 742f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 743f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070 744f7917c00SJeff Kirsher 745f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 746f7917c00SJeff Kirsher * Register 0x0100: SERDES 3125 Configuration Register 1 747f7917c00SJeff Kirsher * Bit 10 RXEQB_3 748f7917c00SJeff Kirsher * Bit 8 RXEQB_2 749f7917c00SJeff Kirsher * Bit 6 RXEQB_1 750f7917c00SJeff Kirsher * Bit 4 RXEQB_0 751f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 752f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0 753f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXEQB_3 10 754f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXEQB_2 8 755f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXEQB_1 6 756f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXEQB_0 4 757f7917c00SJeff Kirsher 758f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 759f7917c00SJeff Kirsher * Register 0x0101: SERDES 3125 Configuration Register 2 760f7917c00SJeff Kirsher * Bit 12 YSEL 761f7917c00SJeff Kirsher * Bit 7 PRE_EMPH_3 762f7917c00SJeff Kirsher * Bit 6 PRE_EMPH_2 763f7917c00SJeff Kirsher * Bit 5 PRE_EMPH_1 764f7917c00SJeff Kirsher * Bit 4 PRE_EMPH_0 765f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 766f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_YSEL 0x1000 767f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0 768f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080 769f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040 770f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020 771f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010 772f7917c00SJeff Kirsher 773f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 774f7917c00SJeff Kirsher * Register 0x0102: SERDES 3125 Interrupt Enable Register 775f7917c00SJeff Kirsher * Bit 3 LASIE 776f7917c00SJeff Kirsher * Bit 2 SPLL_RAE 777f7917c00SJeff Kirsher * Bit 1 MPLL_RAE 778f7917c00SJeff Kirsher * Bit 0 PLL_LOCKE 779f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 780f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LASIE 0x0008 781f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004 782f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002 783f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001 784f7917c00SJeff Kirsher 785f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 786f7917c00SJeff Kirsher * Register 0x0103: SERDES 3125 Interrupt Visibility Register 787f7917c00SJeff Kirsher * Bit 3 LASIV 788f7917c00SJeff Kirsher * Bit 2 SPLL_RAV 789f7917c00SJeff Kirsher * Bit 1 MPLL_RAV 790f7917c00SJeff Kirsher * Bit 0 PLL_LOCKV 791f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 792f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LASIV 0x0008 793f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004 794f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002 795f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001 796f7917c00SJeff Kirsher 797f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 798f7917c00SJeff Kirsher * Register 0x0104: SERDES 3125 Interrupt Status Register 799f7917c00SJeff Kirsher * Bit 3 LASII 800f7917c00SJeff Kirsher * Bit 2 SPLL_RAI 801f7917c00SJeff Kirsher * Bit 1 MPLL_RAI 802f7917c00SJeff Kirsher * Bit 0 PLL_LOCKI 803f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 804f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LASII 0x0008 805f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004 806f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002 807f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001 808f7917c00SJeff Kirsher 809f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 810f7917c00SJeff Kirsher * Register 0x0107: SERDES 3125 Test Configuration 811f7917c00SJeff Kirsher * Bit 12 DUALTX 812f7917c00SJeff Kirsher * Bit 10 HC_1 813f7917c00SJeff Kirsher * Bit 9 HC_0 814f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 815f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_DUALTX 0x1000 816f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HC 0x0600 817f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_HC_0 9 818f7917c00SJeff Kirsher 819f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 820f7917c00SJeff Kirsher * Register 0x2040: RXXG Configuration 1 821f7917c00SJeff Kirsher * Bit 15 RXXG_RXEN 822f7917c00SJeff Kirsher * Bit 14 RXXG_ROCF 823f7917c00SJeff Kirsher * Bit 13 RXXG_PAD_STRIP 824f7917c00SJeff Kirsher * Bit 10 RXXG_PUREP 825f7917c00SJeff Kirsher * Bit 9 RXXG_LONGP 826f7917c00SJeff Kirsher * Bit 8 RXXG_PARF 827f7917c00SJeff Kirsher * Bit 7 RXXG_FLCHK 828f7917c00SJeff Kirsher * Bit 5 RXXG_PASS_CTRL 829f7917c00SJeff Kirsher * Bit 3 RXXG_CRC_STRIP 830f7917c00SJeff Kirsher * Bit 2-0 RXXG_MIFG 831f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 832f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000 833f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000 834f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000 835f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400 836f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200 837f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100 838f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080 839f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020 840f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008 841f7917c00SJeff Kirsher 842f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 843f7917c00SJeff Kirsher * Register 0x02041: RXXG Configuration 2 844f7917c00SJeff Kirsher * Bit 7-0 RXXG_HDRSIZE 845f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 846f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF 847f7917c00SJeff Kirsher 848f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 849f7917c00SJeff Kirsher * Register 0x2042: RXXG Configuration 3 850f7917c00SJeff Kirsher * Bit 15 RXXG_MIN_LERRE 851f7917c00SJeff Kirsher * Bit 14 RXXG_MAX_LERRE 852f7917c00SJeff Kirsher * Bit 12 RXXG_LINE_ERRE 853f7917c00SJeff Kirsher * Bit 10 RXXG_RX_OVRE 854f7917c00SJeff Kirsher * Bit 9 RXXG_ADR_FILTERE 855f7917c00SJeff Kirsher * Bit 8 RXXG_ERR_FILTERE 856f7917c00SJeff Kirsher * Bit 5 RXXG_PRMB_ERRE 857f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 858f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000 859f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000 860f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000 861f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400 862f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200 863f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100 864f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 865f7917c00SJeff Kirsher 866f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 867f7917c00SJeff Kirsher * Register 0x2043: RXXG Interrupt 868f7917c00SJeff Kirsher * Bit 15 RXXG_MIN_LERRI 869f7917c00SJeff Kirsher * Bit 14 RXXG_MAX_LERRI 870f7917c00SJeff Kirsher * Bit 12 RXXG_LINE_ERRI 871f7917c00SJeff Kirsher * Bit 10 RXXG_RX_OVRI 872f7917c00SJeff Kirsher * Bit 9 RXXG_ADR_FILTERI 873f7917c00SJeff Kirsher * Bit 8 RXXG_ERR_FILTERI 874f7917c00SJeff Kirsher * Bit 5 RXXG_PRMB_ERRE 875f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 876f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000 877f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000 878f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000 879f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400 880f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200 881f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100 882f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 883f7917c00SJeff Kirsher 884f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 885f7917c00SJeff Kirsher * Register 0x2049: RXXG Receive FIFO Threshold 886f7917c00SJeff Kirsher * Bit 2-0 RXXG_CUT_THRU 887f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 888f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007 889f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0 890f7917c00SJeff Kirsher 891f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 892f7917c00SJeff Kirsher * Register 0x2062H - 0x2069: RXXG Exact Match VID 893f7917c00SJeff Kirsher * Bit 11-0 RXXG_VID_MATCH 894f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 895f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF 896f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0 897f7917c00SJeff Kirsher 898f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 899f7917c00SJeff Kirsher * Register 0x206EH - 0x206F: RXXG Address Filter Control 900f7917c00SJeff Kirsher * Bit 3 RXXG_FORWARD_ENABLE 901f7917c00SJeff Kirsher * Bit 2 RXXG_VLAN_ENABLE 902f7917c00SJeff Kirsher * Bit 1 RXXG_SRC_ADDR 903f7917c00SJeff Kirsher * Bit 0 RXXG_MATCH_ENABLE 904f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 905f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008 906f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004 907f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002 908f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001 909f7917c00SJeff Kirsher 910f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 911f7917c00SJeff Kirsher * Register 0x2070: RXXG Address Filter Control 2 912f7917c00SJeff Kirsher * Bit 1 RXXG_PMODE 913f7917c00SJeff Kirsher * Bit 0 RXXG_MHASH_EN 914f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 915f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002 916f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001 917f7917c00SJeff Kirsher 918f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 919f7917c00SJeff Kirsher * Register 0x2081: XRF Control Register 2 920f7917c00SJeff Kirsher * Bit 6 EN_PKT_GEN 921f7917c00SJeff Kirsher * Bit 4-2 PATT 922f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 923f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040 924f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PATT 0x001C 925f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PATT 2 926f7917c00SJeff Kirsher 927f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 928f7917c00SJeff Kirsher * Register 0x2088: XRF Interrupt Enable 929f7917c00SJeff Kirsher * Bit 12-9 LANE_HICERE 930f7917c00SJeff Kirsher * Bit 8-5 HS_SD_LANEE 931f7917c00SJeff Kirsher * Bit 4 ALIGN_STATUS_ERRE 932f7917c00SJeff Kirsher * Bit 3-0 LANE_SYNC_STAT_ERRE 933f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 934f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00 935f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_HICERE 9 936f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0 937f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5 938f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010 939f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F 940f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0 941f7917c00SJeff Kirsher 942f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 943f7917c00SJeff Kirsher * Register 0x2089: XRF Interrupt Status 944f7917c00SJeff Kirsher * Bit 12-9 LANE_HICERI 945f7917c00SJeff Kirsher * Bit 8-5 HS_SD_LANEI 946f7917c00SJeff Kirsher * Bit 4 ALIGN_STATUS_ERRI 947f7917c00SJeff Kirsher * Bit 3-0 LANE_SYNC_STAT_ERRI 948f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 949f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00 950f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_HICERI 9 951f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0 952f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5 953f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010 954f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F 955f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0 956f7917c00SJeff Kirsher 957f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 958f7917c00SJeff Kirsher * Register 0x208A: XRF Error Status 959f7917c00SJeff Kirsher * Bit 8-5 HS_SD_LANE 960f7917c00SJeff Kirsher * Bit 4 ALIGN_STATUS_ERR 961f7917c00SJeff Kirsher * Bit 3-0 LANE_SYNC_STAT_ERR 962f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 963f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100 964f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080 965f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040 966f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020 967f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010 968f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008 969f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004 970f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002 971f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001 972f7917c00SJeff Kirsher 973f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 974f7917c00SJeff Kirsher * Register 0x208B: XRF Diagnostic Interrupt Enable 975f7917c00SJeff Kirsher * Bit 7-4 LANE_OVERRUNE 976f7917c00SJeff Kirsher * Bit 3-0 LANE_UNDERRUNE 977f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 978f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0 979f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4 980f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F 981f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0 982f7917c00SJeff Kirsher 983f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 984f7917c00SJeff Kirsher * Register 0x208C: XRF Diagnostic Interrupt Status 985f7917c00SJeff Kirsher * Bit 7-4 LANE_OVERRUNI 986f7917c00SJeff Kirsher * Bit 3-0 LANE_UNDERRUNI 987f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 988f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0 989f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4 990f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F 991f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0 992f7917c00SJeff Kirsher 993f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 994f7917c00SJeff Kirsher * Register 0x20C0: RXOAM Configuration 995f7917c00SJeff Kirsher * Bit 15 RXOAM_BUSY 996f7917c00SJeff Kirsher * Bit 14-12 RXOAM_F2_SEL 997f7917c00SJeff Kirsher * Bit 10-8 RXOAM_F1_SEL 998f7917c00SJeff Kirsher * Bit 7-6 RXOAM_FILTER_CTRL 999f7917c00SJeff Kirsher * Bit 5-0 RXOAM_PX_EN 1000f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1001f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000 1002f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000 1003f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12 1004f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700 1005f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8 1006f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0 1007f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6 1008f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F 1009f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0 1010f7917c00SJeff Kirsher 1011f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1012f7917c00SJeff Kirsher * Register 0x20C1,0x20C2: RXOAM Filter Configuration 1013f7917c00SJeff Kirsher * Bit 15-8 RXOAM_FX_MASK 1014f7917c00SJeff Kirsher * Bit 7-0 RXOAM_FX_VAL 1015f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1016f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00 1017f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8 1018f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF 1019f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0 1020f7917c00SJeff Kirsher 1021f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1022f7917c00SJeff Kirsher * Register 0x20C3: RXOAM Configuration Register 2 1023f7917c00SJeff Kirsher * Bit 13 RXOAM_REC_BYTE_VAL 1024f7917c00SJeff Kirsher * Bit 11-10 RXOAM_BYPASS_MODE 1025f7917c00SJeff Kirsher * Bit 5-0 RXOAM_PX_CLEAR 1026f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1027f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000 1028f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00 1029f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10 1030f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F 1031f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0 1032f7917c00SJeff Kirsher 1033f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1034f7917c00SJeff Kirsher * Register 0x20C4: RXOAM HEC Configuration 1035f7917c00SJeff Kirsher * Bit 15-8 RXOAM_COSET 1036f7917c00SJeff Kirsher * Bit 2 RXOAM_HEC_ERR_PKT 1037f7917c00SJeff Kirsher * Bit 0 RXOAM_HEC_EN 1038f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1039f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00 1040f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8 1041f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004 1042f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001 1043f7917c00SJeff Kirsher 1044f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1045f7917c00SJeff Kirsher * Register 0x20C7: RXOAM Interrupt Enable 1046f7917c00SJeff Kirsher * Bit 10 RXOAM_FILTER_THRSHE 1047f7917c00SJeff Kirsher * Bit 9 RXOAM_OAM_ERRE 1048f7917c00SJeff Kirsher * Bit 8 RXOAM_HECE_THRSHE 1049f7917c00SJeff Kirsher * Bit 7 RXOAM_SOPE 1050f7917c00SJeff Kirsher * Bit 6 RXOAM_RFE 1051f7917c00SJeff Kirsher * Bit 5 RXOAM_LFE 1052f7917c00SJeff Kirsher * Bit 4 RXOAM_DV_ERRE 1053f7917c00SJeff Kirsher * Bit 3 RXOAM_DATA_INVALIDE 1054f7917c00SJeff Kirsher * Bit 2 RXOAM_FILTER_DROPE 1055f7917c00SJeff Kirsher * Bit 1 RXOAM_HECE 1056f7917c00SJeff Kirsher * Bit 0 RXOAM_OFLE 1057f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1058f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400 1059f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200 1060f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100 1061f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080 1062f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040 1063f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020 1064f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010 1065f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008 1066f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004 1067f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002 1068f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001 1069f7917c00SJeff Kirsher 1070f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1071f7917c00SJeff Kirsher * Register 0x20C8: RXOAM Interrupt Status 1072f7917c00SJeff Kirsher * Bit 10 RXOAM_FILTER_THRSHI 1073f7917c00SJeff Kirsher * Bit 9 RXOAM_OAM_ERRI 1074f7917c00SJeff Kirsher * Bit 8 RXOAM_HECE_THRSHI 1075f7917c00SJeff Kirsher * Bit 7 RXOAM_SOPI 1076f7917c00SJeff Kirsher * Bit 6 RXOAM_RFI 1077f7917c00SJeff Kirsher * Bit 5 RXOAM_LFI 1078f7917c00SJeff Kirsher * Bit 4 RXOAM_DV_ERRI 1079f7917c00SJeff Kirsher * Bit 3 RXOAM_DATA_INVALIDI 1080f7917c00SJeff Kirsher * Bit 2 RXOAM_FILTER_DROPI 1081f7917c00SJeff Kirsher * Bit 1 RXOAM_HECI 1082f7917c00SJeff Kirsher * Bit 0 RXOAM_OFLI 1083f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1084f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400 1085f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200 1086f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100 1087f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080 1088f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040 1089f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020 1090f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010 1091f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008 1092f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004 1093f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002 1094f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001 1095f7917c00SJeff Kirsher 1096f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1097f7917c00SJeff Kirsher * Register 0x20C9: RXOAM Status 1098f7917c00SJeff Kirsher * Bit 10 RXOAM_FILTER_THRSHV 1099f7917c00SJeff Kirsher * Bit 8 RXOAM_HECE_THRSHV 1100f7917c00SJeff Kirsher * Bit 6 RXOAM_RFV 1101f7917c00SJeff Kirsher * Bit 5 RXOAM_LFV 1102f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1103f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400 1104f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100 1105f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040 1106f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020 1107f7917c00SJeff Kirsher 1108f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1109f7917c00SJeff Kirsher * Register 0x2100: MSTAT Control 1110f7917c00SJeff Kirsher * Bit 2 MSTAT_WRITE 1111f7917c00SJeff Kirsher * Bit 1 MSTAT_CLEAR 1112f7917c00SJeff Kirsher * Bit 0 MSTAT_SNAP 1113f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1114f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004 1115f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002 1116f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001 1117f7917c00SJeff Kirsher 1118f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1119f7917c00SJeff Kirsher * Register 0x2109: MSTAT Counter Write Address 1120f7917c00SJeff Kirsher * Bit 5-0 MSTAT_WRITE_ADDRESS 1121f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1122f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F 1123f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0 1124f7917c00SJeff Kirsher 1125f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1126f7917c00SJeff Kirsher * Register 0x2200: IFLX Global Configuration Register 1127f7917c00SJeff Kirsher * Bit 15 IFLX_IRCU_ENABLE 1128f7917c00SJeff Kirsher * Bit 14 IFLX_IDSWT_ENABLE 1129f7917c00SJeff Kirsher * Bit 13-0 IFLX_IFD_CNT 1130f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1131f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000 1132f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000 1133f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF 1134f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0 1135f7917c00SJeff Kirsher 1136f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1137f7917c00SJeff Kirsher * Register 0x2209: IFLX FIFO Overflow Enable 1138f7917c00SJeff Kirsher * Bit 0 IFLX_OVFE 1139f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1140f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001 1141f7917c00SJeff Kirsher 1142f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1143f7917c00SJeff Kirsher * Register 0x220A: IFLX FIFO Overflow Interrupt 1144f7917c00SJeff Kirsher * Bit 0 IFLX_OVFI 1145f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1146f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001 1147f7917c00SJeff Kirsher 1148f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1149f7917c00SJeff Kirsher * Register 0x220D: IFLX Indirect Channel Address 1150f7917c00SJeff Kirsher * Bit 15 IFLX_BUSY 1151f7917c00SJeff Kirsher * Bit 14 IFLX_RWB 1152f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1153f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000 1154f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000 1155f7917c00SJeff Kirsher 1156f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1157f7917c00SJeff Kirsher * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision 1158f7917c00SJeff Kirsher * Bit 9-0 IFLX_LOLIM 1159f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1160f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF 1161f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0 1162f7917c00SJeff Kirsher 1163f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1164f7917c00SJeff Kirsher * Register 0x220F: IFLX Indirect Logical FIFO High Limit 1165f7917c00SJeff Kirsher * Bit 9-0 IFLX_HILIM 1166f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1167f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF 1168f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0 1169f7917c00SJeff Kirsher 1170f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1171f7917c00SJeff Kirsher * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit 1172f7917c00SJeff Kirsher * Bit 15 IFLX_FULL 1173f7917c00SJeff Kirsher * Bit 14 IFLX_AFULL 1174f7917c00SJeff Kirsher * Bit 13-0 IFLX_AFTH 1175f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1176f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000 1177f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000 1178f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF 1179f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0 1180f7917c00SJeff Kirsher 1181f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1182f7917c00SJeff Kirsher * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit 1183f7917c00SJeff Kirsher * Bit 15 IFLX_EMPTY 1184f7917c00SJeff Kirsher * Bit 14 IFLX_AEMPTY 1185f7917c00SJeff Kirsher * Bit 13-0 IFLX_AETH 1186f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1187f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000 1188f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000 1189f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF 1190f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_IFLX_AETH 0 1191f7917c00SJeff Kirsher 1192f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1193f7917c00SJeff Kirsher * Register 0x2240: PL4MOS Configuration Register 1194f7917c00SJeff Kirsher * Bit 3 PL4MOS_RE_INIT 1195f7917c00SJeff Kirsher * Bit 2 PL4MOS_EN 1196f7917c00SJeff Kirsher * Bit 1 PL4MOS_NO_STATUS 1197f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1198f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008 1199f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004 1200f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002 1201f7917c00SJeff Kirsher 1202f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1203f7917c00SJeff Kirsher * Register 0x2243: PL4MOS MaxBurst1 Register 1204f7917c00SJeff Kirsher * Bit 11-0 PL4MOS_MAX_BURST1 1205f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1206f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF 1207f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0 1208f7917c00SJeff Kirsher 1209f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1210f7917c00SJeff Kirsher * Register 0x2244: PL4MOS MaxBurst2 Register 1211f7917c00SJeff Kirsher * Bit 11-0 PL4MOS_MAX_BURST2 1212f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1213f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF 1214f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0 1215f7917c00SJeff Kirsher 1216f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1217f7917c00SJeff Kirsher * Register 0x2245: PL4MOS Transfer Size Register 1218f7917c00SJeff Kirsher * Bit 7-0 PL4MOS_MAX_TRANSFER 1219f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1220f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF 1221f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0 1222f7917c00SJeff Kirsher 1223f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1224f7917c00SJeff Kirsher * Register 0x2280: PL4ODP Configuration 1225f7917c00SJeff Kirsher * Bit 15-12 PL4ODP_REPEAT_T 1226f7917c00SJeff Kirsher * Bit 8 PL4ODP_SOP_RULE 1227f7917c00SJeff Kirsher * Bit 1 PL4ODP_EN_PORTS 1228f7917c00SJeff Kirsher * Bit 0 PL4ODP_EN_DFWD 1229f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1230f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000 1231f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12 1232f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100 1233f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002 1234f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001 1235f7917c00SJeff Kirsher 1236f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1237f7917c00SJeff Kirsher * Register 0x2282: PL4ODP Interrupt Mask 1238f7917c00SJeff Kirsher * Bit 0 PL4ODP_OUT_DISE 1239f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1240f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001 1241f7917c00SJeff Kirsher 1242f7917c00SJeff Kirsher 1243f7917c00SJeff Kirsher 1244f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080 1245f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040 1246f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008 1247f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004 1248f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002 1249f7917c00SJeff Kirsher 1250f7917c00SJeff Kirsher 1251f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1252f7917c00SJeff Kirsher * Register 0x2283: PL4ODP Interrupt 1253f7917c00SJeff Kirsher * Bit 0 PL4ODP_OUT_DISI 1254f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1255f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001 1256f7917c00SJeff Kirsher 1257f7917c00SJeff Kirsher 1258f7917c00SJeff Kirsher 1259f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080 1260f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040 1261f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008 1262f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004 1263f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002 1264f7917c00SJeff Kirsher 1265f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1266f7917c00SJeff Kirsher * Register 0x2300: PL4IO Lock Detect Status 1267f7917c00SJeff Kirsher * Bit 15 PL4IO_OUT_ROOLV 1268f7917c00SJeff Kirsher * Bit 12 PL4IO_IS_ROOLV 1269f7917c00SJeff Kirsher * Bit 11 PL4IO_DIP2_ERRV 1270f7917c00SJeff Kirsher * Bit 8 PL4IO_ID_ROOLV 1271f7917c00SJeff Kirsher * Bit 4 PL4IO_IS_DOOLV 1272f7917c00SJeff Kirsher * Bit 0 PL4IO_ID_DOOLV 1273f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1274f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000 1275f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000 1276f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800 1277f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100 1278f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010 1279f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001 1280f7917c00SJeff Kirsher 1281f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1282f7917c00SJeff Kirsher * Register 0x2301: PL4IO Lock Detect Change 1283f7917c00SJeff Kirsher * Bit 15 PL4IO_OUT_ROOLI 1284f7917c00SJeff Kirsher * Bit 12 PL4IO_IS_ROOLI 1285f7917c00SJeff Kirsher * Bit 11 PL4IO_DIP2_ERRI 1286f7917c00SJeff Kirsher * Bit 8 PL4IO_ID_ROOLI 1287f7917c00SJeff Kirsher * Bit 4 PL4IO_IS_DOOLI 1288f7917c00SJeff Kirsher * Bit 0 PL4IO_ID_DOOLI 1289f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1290f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000 1291f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000 1292f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800 1293f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100 1294f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010 1295f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001 1296f7917c00SJeff Kirsher 1297f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1298f7917c00SJeff Kirsher * Register 0x2302: PL4IO Lock Detect Mask 1299f7917c00SJeff Kirsher * Bit 15 PL4IO_OUT_ROOLE 1300f7917c00SJeff Kirsher * Bit 12 PL4IO_IS_ROOLE 1301f7917c00SJeff Kirsher * Bit 11 PL4IO_DIP2_ERRE 1302f7917c00SJeff Kirsher * Bit 8 PL4IO_ID_ROOLE 1303f7917c00SJeff Kirsher * Bit 4 PL4IO_IS_DOOLE 1304f7917c00SJeff Kirsher * Bit 0 PL4IO_ID_DOOLE 1305f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1306f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000 1307f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000 1308f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800 1309f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100 1310f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010 1311f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001 1312f7917c00SJeff Kirsher 1313f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1314f7917c00SJeff Kirsher * Register 0x2303: PL4IO Lock Detect Limits 1315f7917c00SJeff Kirsher * Bit 15-8 PL4IO_REF_LIMIT 1316f7917c00SJeff Kirsher * Bit 7-0 PL4IO_TRAN_LIMIT 1317f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1318f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00 1319f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8 1320f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF 1321f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0 1322f7917c00SJeff Kirsher 1323f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1324f7917c00SJeff Kirsher * Register 0x2304: PL4IO Calendar Repetitions 1325f7917c00SJeff Kirsher * Bit 15-8 PL4IO_IN_MUL 1326f7917c00SJeff Kirsher * Bit 7-0 PL4IO_OUT_MUL 1327f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1328f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00 1329f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8 1330f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF 1331f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0 1332f7917c00SJeff Kirsher 1333f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1334f7917c00SJeff Kirsher * Register 0x2305: PL4IO Configuration 1335f7917c00SJeff Kirsher * Bit 15 PL4IO_DIP2_ERR_CHK 1336f7917c00SJeff Kirsher * Bit 11 PL4IO_ODAT_DIS 1337f7917c00SJeff Kirsher * Bit 10 PL4IO_TRAIN_DIS 1338f7917c00SJeff Kirsher * Bit 9 PL4IO_OSTAT_DIS 1339f7917c00SJeff Kirsher * Bit 8 PL4IO_ISTAT_DIS 1340f7917c00SJeff Kirsher * Bit 7 PL4IO_NO_ISTAT 1341f7917c00SJeff Kirsher * Bit 6 PL4IO_STAT_OUTSEL 1342f7917c00SJeff Kirsher * Bit 5 PL4IO_INSEL 1343f7917c00SJeff Kirsher * Bit 4 PL4IO_DLSEL 1344f7917c00SJeff Kirsher * Bit 1-0 PL4IO_OUTSEL 1345f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1346f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000 1347f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800 1348f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400 1349f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200 1350f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100 1351f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080 1352f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040 1353f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020 1354f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010 1355f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003 1356f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0 1357f7917c00SJeff Kirsher 1358f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1359f7917c00SJeff Kirsher * Register 0x3040: TXXG Configuration Register 1 1360f7917c00SJeff Kirsher * Bit 15 TXXG_TXEN0 1361f7917c00SJeff Kirsher * Bit 13 TXXG_HOSTPAUSE 1362f7917c00SJeff Kirsher * Bit 12-7 TXXG_IPGT 1363f7917c00SJeff Kirsher * Bit 5 TXXG_32BIT_ALIGN 1364f7917c00SJeff Kirsher * Bit 4 TXXG_CRCEN 1365f7917c00SJeff Kirsher * Bit 3 TXXG_FCTX 1366f7917c00SJeff Kirsher * Bit 2 TXXG_FCRX 1367f7917c00SJeff Kirsher * Bit 1 TXXG_PADEN 1368f7917c00SJeff Kirsher * Bit 0 TXXG_SPRE 1369f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1370f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000 1371f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000 1372f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80 1373f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7 1374f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020 1375f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010 1376f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008 1377f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004 1378f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002 1379f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001 1380f7917c00SJeff Kirsher 1381f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1382f7917c00SJeff Kirsher * Register 0x3041: TXXG Configuration Register 2 1383f7917c00SJeff Kirsher * Bit 7-0 TXXG_HDRSIZE 1384f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1385f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF 1386f7917c00SJeff Kirsher 1387f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1388f7917c00SJeff Kirsher * Register 0x3042: TXXG Configuration Register 3 1389f7917c00SJeff Kirsher * Bit 15 TXXG_FIFO_ERRE 1390f7917c00SJeff Kirsher * Bit 14 TXXG_FIFO_UDRE 1391f7917c00SJeff Kirsher * Bit 13 TXXG_MAX_LERRE 1392f7917c00SJeff Kirsher * Bit 12 TXXG_MIN_LERRE 1393f7917c00SJeff Kirsher * Bit 11 TXXG_XFERE 1394f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1395f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000 1396f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000 1397f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000 1398f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000 1399f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800 1400f7917c00SJeff Kirsher 1401f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1402f7917c00SJeff Kirsher * Register 0x3043: TXXG Interrupt 1403f7917c00SJeff Kirsher * Bit 15 TXXG_FIFO_ERRI 1404f7917c00SJeff Kirsher * Bit 14 TXXG_FIFO_UDRI 1405f7917c00SJeff Kirsher * Bit 13 TXXG_MAX_LERRI 1406f7917c00SJeff Kirsher * Bit 12 TXXG_MIN_LERRI 1407f7917c00SJeff Kirsher * Bit 11 TXXG_XFERI 1408f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1409f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000 1410f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000 1411f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000 1412f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000 1413f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800 1414f7917c00SJeff Kirsher 1415f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1416f7917c00SJeff Kirsher * Register 0x3044: TXXG Status Register 1417f7917c00SJeff Kirsher * Bit 1 TXXG_TXACTIVE 1418f7917c00SJeff Kirsher * Bit 0 TXXG_PAUSED 1419f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1420f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002 1421f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001 1422f7917c00SJeff Kirsher 1423f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1424f7917c00SJeff Kirsher * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register 1425f7917c00SJeff Kirsher * Bit 7-0 TXXG_TX_MINFR 1426f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1427f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF 1428f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0 1429f7917c00SJeff Kirsher 1430f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1431f7917c00SJeff Kirsher * Register 0x3052: TXXG Pause Quantum Value Configuration Register 1432f7917c00SJeff Kirsher * Bit 7-0 TXXG_FC_PAUSE_QNTM 1433f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1434f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF 1435f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0 1436f7917c00SJeff Kirsher 1437f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1438f7917c00SJeff Kirsher * Register 0x3080: XTEF Control 1439f7917c00SJeff Kirsher * Bit 3-0 XTEF_FORCE_PARITY_ERR 1440f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1441f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F 1442f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0 1443f7917c00SJeff Kirsher 1444f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1445f7917c00SJeff Kirsher * Register 0x3084: XTEF Interrupt Event Register 1446f7917c00SJeff Kirsher * Bit 0 XTEF_LOST_SYNCI 1447f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1448f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001 1449f7917c00SJeff Kirsher 1450f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1451f7917c00SJeff Kirsher * Register 0x3085: XTEF Interrupt Enable Register 1452f7917c00SJeff Kirsher * Bit 0 XTEF_LOST_SYNCE 1453f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1454f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001 1455f7917c00SJeff Kirsher 1456f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1457f7917c00SJeff Kirsher * Register 0x3086: XTEF Visibility Register 1458f7917c00SJeff Kirsher * Bit 0 XTEF_LOST_SYNCV 1459f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1460f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001 1461f7917c00SJeff Kirsher 1462f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1463f7917c00SJeff Kirsher * Register 0x30C0: TXOAM OAM Configuration 1464f7917c00SJeff Kirsher * Bit 15 TXOAM_HEC_EN 1465f7917c00SJeff Kirsher * Bit 14 TXOAM_EMPTYCODE_EN 1466f7917c00SJeff Kirsher * Bit 13 TXOAM_FORCE_IDLE 1467f7917c00SJeff Kirsher * Bit 12 TXOAM_IGNORE_IDLE 1468f7917c00SJeff Kirsher * Bit 11-6 TXOAM_PX_OVERWRITE 1469f7917c00SJeff Kirsher * Bit 5-0 TXOAM_PX_SEL 1470f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1471f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000 1472f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000 1473f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000 1474f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000 1475f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0 1476f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6 1477f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F 1478f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0 1479f7917c00SJeff Kirsher 1480f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1481f7917c00SJeff Kirsher * Register 0x30C1: TXOAM Mini-Packet Rate Configuration 1482f7917c00SJeff Kirsher * Bit 15 TXOAM_MINIDIS 1483f7917c00SJeff Kirsher * Bit 14 TXOAM_BUSY 1484f7917c00SJeff Kirsher * Bit 13 TXOAM_TRANS_EN 1485f7917c00SJeff Kirsher * Bit 10-0 TXOAM_MINIRATE 1486f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1487f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000 1488f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000 1489f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000 1490f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF 1491f7917c00SJeff Kirsher 1492f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1493f7917c00SJeff Kirsher * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration 1494f7917c00SJeff Kirsher * Bit 13-10 TXOAM_FTHRESH 1495f7917c00SJeff Kirsher * Bit 9-6 TXOAM_MINIPOST 1496f7917c00SJeff Kirsher * Bit 5-0 TXOAM_MINIPRE 1497f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1498f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00 1499f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10 1500f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0 1501f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6 1502f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F 1503f7917c00SJeff Kirsher 1504f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1505f7917c00SJeff Kirsher * Register 0x30C6: TXOAM Interrupt Enable 1506f7917c00SJeff Kirsher * Bit 2 TXOAM_SOP_ERRE 1507f7917c00SJeff Kirsher * Bit 1 TXOAM_OFLE 1508f7917c00SJeff Kirsher * Bit 0 TXOAM_ERRE 1509f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1510f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004 1511f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002 1512f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001 1513f7917c00SJeff Kirsher 1514f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1515f7917c00SJeff Kirsher * Register 0x30C7: TXOAM Interrupt Status 1516f7917c00SJeff Kirsher * Bit 2 TXOAM_SOP_ERRI 1517f7917c00SJeff Kirsher * Bit 1 TXOAM_OFLI 1518f7917c00SJeff Kirsher * Bit 0 TXOAM_ERRI 1519f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1520f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004 1521f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002 1522f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001 1523f7917c00SJeff Kirsher 1524f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1525f7917c00SJeff Kirsher * Register 0x30CF: TXOAM Coset 1526f7917c00SJeff Kirsher * Bit 7-0 TXOAM_COSET 1527f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1528f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF 1529f7917c00SJeff Kirsher 1530f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1531f7917c00SJeff Kirsher * Register 0x3200: EFLX Global Configuration 1532f7917c00SJeff Kirsher * Bit 15 EFLX_ERCU_EN 1533f7917c00SJeff Kirsher * Bit 7 EFLX_EN_EDSWT 1534f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1535f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000 1536f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080 1537f7917c00SJeff Kirsher 1538f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1539f7917c00SJeff Kirsher * Register 0x3201: EFLX ERCU Global Status 1540f7917c00SJeff Kirsher * Bit 13 EFLX_OVF_ERR 1541f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1542f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000 1543f7917c00SJeff Kirsher 1544f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1545f7917c00SJeff Kirsher * Register 0x3202: EFLX Indirect Channel Address 1546f7917c00SJeff Kirsher * Bit 15 EFLX_BUSY 1547f7917c00SJeff Kirsher * Bit 14 EFLX_RDWRB 1548f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1549f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000 1550f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000 1551f7917c00SJeff Kirsher 1552f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1553f7917c00SJeff Kirsher * Register 0x3203: EFLX Indirect Logical FIFO Low Limit 1554f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1555f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF 1556f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0 1557f7917c00SJeff Kirsher 1558f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1559f7917c00SJeff Kirsher * Register 0x3204: EFLX Indirect Logical FIFO High Limit 1560f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1561f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF 1562f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0 1563f7917c00SJeff Kirsher 1564f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1565f7917c00SJeff Kirsher * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit 1566f7917c00SJeff Kirsher * Bit 15 EFLX_FULL 1567f7917c00SJeff Kirsher * Bit 14 EFLX_AFULL 1568f7917c00SJeff Kirsher * Bit 13-0 EFLX_AFTH 1569f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1570f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000 1571f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000 1572f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF 1573f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0 1574f7917c00SJeff Kirsher 1575f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1576f7917c00SJeff Kirsher * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit 1577f7917c00SJeff Kirsher * Bit 15 EFLX_EMPTY 1578f7917c00SJeff Kirsher * Bit 14 EFLX_AEMPTY 1579f7917c00SJeff Kirsher * Bit 13-0 EFLX_AETH 1580f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1581f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000 1582f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000 1583f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF 1584f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_EFLX_AETH 0 1585f7917c00SJeff Kirsher 1586f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1587f7917c00SJeff Kirsher * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold 1588f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1589f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF 1590f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0 1591f7917c00SJeff Kirsher 1592f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1593f7917c00SJeff Kirsher * Register 0x320C: EFLX FIFO Overflow Error Enable 1594f7917c00SJeff Kirsher * Bit 0 EFLX_OVFE 1595f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1596f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001 1597f7917c00SJeff Kirsher 1598f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1599f7917c00SJeff Kirsher * Register 0x320D: EFLX FIFO Overflow Error Indication 1600f7917c00SJeff Kirsher * Bit 0 EFLX_OVFI 1601f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1602f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001 1603f7917c00SJeff Kirsher 1604f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1605f7917c00SJeff Kirsher * Register 0x3210: EFLX Channel Provision 1606f7917c00SJeff Kirsher * Bit 0 EFLX_PROV 1607f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1608f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001 1609f7917c00SJeff Kirsher 1610f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1611f7917c00SJeff Kirsher * Register 0x3280: PL4IDU Configuration 1612f7917c00SJeff Kirsher * Bit 2 PL4IDU_SYNCH_ON_TRAIN 1613f7917c00SJeff Kirsher * Bit 1 PL4IDU_EN_PORTS 1614f7917c00SJeff Kirsher * Bit 0 PL4IDU_EN_DFWD 1615f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1616f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004 1617f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002 1618f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001 1619f7917c00SJeff Kirsher 1620f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1621f7917c00SJeff Kirsher * Register 0x3282: PL4IDU Interrupt Mask 1622f7917c00SJeff Kirsher * Bit 1 PL4IDU_DIP4E 1623f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1624f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002 1625f7917c00SJeff Kirsher 1626f7917c00SJeff Kirsher /*---------------------------------------------------------------------------- 1627f7917c00SJeff Kirsher * Register 0x3283: PL4IDU Interrupt 1628f7917c00SJeff Kirsher * Bit 1 PL4IDU_DIP4I 1629f7917c00SJeff Kirsher *----------------------------------------------------------------------------*/ 1630f7917c00SJeff Kirsher #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002 1631f7917c00SJeff Kirsher 1632f7917c00SJeff Kirsher #endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */ 1633