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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qm-apalis.dtsi19 * Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver
33 pinctrl-0 = <&pinctrl_lpi2c0>;
35 #size-cells = <0>;
263 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
264 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
265 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
266 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
267 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
268 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
269 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
[all …]
H A Dimx8dxl-evk.dts27 reg = <0x00000000 0x80000000 0 0x40000000>;
39 * reg = <0 0x96000000 0 0x2000000>;
48 size = <0 0x14000000>;
49 alloc-ranges = <0 0x98000000 0 0x14000000>;
54 mux3_en: regulator-0 {
78 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
119 pinctrl-0 = <&pinctrl_eqos>;
129 #size-cells = <0>;
131 ethphy0: ethernet-phy@0 {
133 reg = <0>;
[all …]
H A Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
82 pinctrl-0 = <&pinctrl_wifi_pdn>;
93 pinctrl-0 = <&pinctrl_gpio7>;
105 pinctrl-0 = <&pinctrl_usbh_en>;
135 reg = <0 0x84000000 0 0x2000000>;
140 reg = <0 0x86000000 0 0x200000>;
145 reg = <0 0x86200000 0 0x200000>;
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
15 {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
[all …]
H A Dddr3_spd.c31 #define SPD_MODULE_MASK 0xf
36 #define SPD_DEV_DENSITY_MASK 0xf
45 #define SPD_COL_NUM_OFF 0
49 #define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
56 #define SPD_BUS_WIDTH_OFF 0
73 #define SPD_TRAS_MSB_MASK 0xf
76 #define SPD_TRC_MSB_MASK 0xf0
86 #define SPD_TFAW_MSB_MASK 0xf
93 #define SPD_ADDR_MAP_MIRROR_OFFS 0
96 #define SPD_RDIMM_RC_NIBBLE_MASK 0xF
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt39 - #size-cells: Must be <0>.
53 tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
55 reg = <0x00000001 0x00000000 0x00000400>,
56 <0x00000001 0x00000460 0x00000020>,
57 <0x00000001 0x00000480 0x00000020>,
58 <0x00000001 0x000004A0 0x00000008>,
59 <0x00000001 0x00000400 0x00000020>,
60 <0x00000001 0x00000420 0x00000020>;
63 interrupts = <0 41 4>, <0 40 4>;
77 #size-cells = <0>;
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c24 #define DS414_GPP_OUT_VAL_HIGH (0)
26 #define DS414_GPP_OUT_POL_LOW (0)
27 #define DS414_GPP_OUT_POL_MID (0)
28 #define DS414_GPP_OUT_POL_HIGH (0)
33 #define DS414_GPP_OUT_ENA_HIGH (~0)
36 0x11111111,
37 0x22221111,
38 0x22222222,
39 0x00000000,
40 0x11110000,
[all …]
/openbmc/u-boot/board/theadorable/
H A Dtheadorable.c25 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
27 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
29 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
30 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
31 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
33 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
34 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
35 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
43 #define STM_I2C_ADDR 0x27
48 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
[all …]
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.h14 #define DDRSS_SS_ID_REV_REG 0x00000000
15 #define DDRSS_SS_CTL_REG 0x00000004
16 #define DDRSS_V2H_CTL_REG 0x00000020
18 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0
22 #define DDRSS_DDRCTL_MSTR 0x00000000
23 #define DDRSS_DDRCTL_STAT 0x00000004
24 #define DDRSS_DDRCTL_MRCTRL0 0x00000010
25 #define DDRSS_DDRCTL_MRCTRL1 0x00000014
26 #define DDRSS_DDRCTL_MRSTAT 0x00000018
27 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
/openbmc/linux/drivers/mfd/
H A Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
/openbmc/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]