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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
15 {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
[all …]
H A Dddr3_spd.c31 #define SPD_MODULE_MASK 0xf
36 #define SPD_DEV_DENSITY_MASK 0xf
45 #define SPD_COL_NUM_OFF 0
49 #define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
56 #define SPD_BUS_WIDTH_OFF 0
73 #define SPD_TRAS_MSB_MASK 0xf
76 #define SPD_TRC_MSB_MASK 0xf0
86 #define SPD_TFAW_MSB_MASK 0xf
93 #define SPD_ADDR_MAP_MIRROR_OFFS 0
96 #define SPD_RDIMM_RC_NIBBLE_MASK 0xF
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt39 - #size-cells: Must be <0>.
53 tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
55 reg = <0x00000001 0x00000000 0x00000400>,
56 <0x00000001 0x00000460 0x00000020>,
57 <0x00000001 0x00000480 0x00000020>,
58 <0x00000001 0x000004A0 0x00000008>,
59 <0x00000001 0x00000400 0x00000020>,
60 <0x00000001 0x00000420 0x00000020>;
63 interrupts = <0 41 4>, <0 40 4>;
77 #size-cells = <0>;
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c24 #define DS414_GPP_OUT_VAL_HIGH (0)
26 #define DS414_GPP_OUT_POL_LOW (0)
27 #define DS414_GPP_OUT_POL_MID (0)
28 #define DS414_GPP_OUT_POL_HIGH (0)
33 #define DS414_GPP_OUT_ENA_HIGH (~0)
36 0x11111111,
37 0x22221111,
38 0x22222222,
39 0x00000000,
40 0x11110000,
[all …]
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.h14 #define DDRSS_SS_ID_REV_REG 0x00000000
15 #define DDRSS_SS_CTL_REG 0x00000004
16 #define DDRSS_V2H_CTL_REG 0x00000020
18 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0
22 #define DDRSS_DDRCTL_MSTR 0x00000000
23 #define DDRSS_DDRCTL_STAT 0x00000004
24 #define DDRSS_DDRCTL_MRCTRL0 0x00000010
25 #define DDRSS_DDRCTL_MRCTRL1 0x00000014
26 #define DDRSS_DDRCTL_MRSTAT 0x00000018
27 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbnx2.h30 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
40 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
57 #define RX_BD_FLAGS_NOPUSH (1<<0)
71 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
279 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
321 #define BNX2_L2CTX_TYPE 0x00000000
322 #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323 #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324 #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
327 #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
[all …]