Lines Matching +full:0 +full:x00001420
31 #define SPD_MODULE_MASK 0xf
36 #define SPD_DEV_DENSITY_MASK 0xf
45 #define SPD_COL_NUM_OFF 0
49 #define SPD_MODULE_SDRAM_DEV_WIDTH_OFF 0
56 #define SPD_BUS_WIDTH_OFF 0
73 #define SPD_TRAS_MSB_MASK 0xf
76 #define SPD_TRC_MSB_MASK 0xf0
86 #define SPD_TFAW_MSB_MASK 0xf
93 #define SPD_ADDR_MAP_MIRROR_OFFS 0
96 #define SPD_RDIMM_RC_NIBBLE_MASK 0xF
100 #define SPD_MEM_TYPE_SDRAM 0x4
101 #define SPD_MEM_TYPE_DDR1 0x7
102 #define SPD_MEM_TYPE_DDR2 0x8
103 #define SPD_MEM_TYPE_DDR3 0xB
206 u32 dimm_num = 0; in ddr3_get_dimm_num()
212 data[SPD_DEV_TYPE_BYTE] = 0; in ddr3_get_dimm_num()
215 if ((dimm_num == 0) && (dimm_cur_addr < FAR_END_DIMM_ADDR)) in ddr3_get_dimm_num()
216 return 0; in ddr3_get_dimm_num()
218 ret = i2c_read(dimm_cur_addr, 0, 1, (uchar *)data, 3); in ddr3_get_dimm_num()
237 * Returns: MV_OK if function could read DIMM parameters, 0 otherwise.
247 if (dimm_addr != 0) { in ddr3_spd_init()
248 memset(spd_data, 0, SPD_SIZE * sizeof(u8)); in ddr3_spd_init()
250 ret = i2c_read(dimm_addr, 0, 1, (uchar *)spd_data, SPD_SIZE); in ddr3_spd_init()
261 info->err_check_type = 0; in ddr3_spd_init()
264 if ((spd_data[SPD_BUS_WIDTH_BYTE] & 0x18) >> 3) in ddr3_spd_init()
314 1 << (3 + ((spd_data[SPD_DEV_DENSITY_BYTE] >> 4) & 0x7)); in ddr3_spd_init()
341 (info->data_width / info->sdram_width) * 0x2) << 16; in ddr3_spd_init()
342 /* 0x2 => 0x100000-1Mbit / 8-bit->byte / 0x10000 */ in ddr3_spd_init()
368 * JEDEC param are 0 <= Tcase <= 85: 7.8uSec, 85 <= Tcase in ddr3_spd_init()
482 DEBUG_INIT_C("DDR3 Training Sequence - Registered DIMM vendor ID 0x", in ddr3_spd_init()
485 info->dimm_rc[0] = RDIMM_RC0; in ddr3_spd_init()
504 * Returns: MV_OK if function could read DIMM parameters, 0 otherwise.
508 if (dimm == 0) { in ddr3_spd_sum_init()
582 u32 dimm_num = 0;
586 __maybe_unused u32 dimm_addr[2] = { 0, 0 };
598 status = ddr3_spd_init(&dimm_info[0], 0, *ddr_width);
605 dimm_info[0].num_of_module_ranks = 1;
606 status = ddr3_spd_sum_init(&dimm_info[0], &sum_info, 0);
613 if (dimm_num == 0) {
625 for (dimm = 0; dimm < dimm_num; dimm++) {
638 cs_num = 0;
643 for (dimm = 0; dimm < dimm_num; dimm++)
653 cs_ena = 0;
658 dimm = 0;
661 for (cs = 0; cs < MAX_CS; cs += 2) {
665 cs_ena |= (0x1 << cs);
667 cs_ena |= (0x3 << cs);
669 cs_ena |= (0x7 << cs);
671 cs_ena |= (0xF << cs);
681 if (cs_ena > 0xF) {
689 /* Check Ratio - '1' - 2:1, '0' - 1:1 */
698 reg = ((((reg >> 1) & 0xE)) | (reg & 0x1)) & 0xF;
701 ddr_clk_time, 0),
704 cl = ddr3_div(sum_info.min_cas_lat_time, ddr_clk_time, 0);
711 /* {0x00001400} - DDR SDRAM Configuration Register */
712 reg = 0x73004000;
714 REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0);
758 stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0,
759 REG_SDRAM_CONFIG_RFRS_MASK, 0, 0);
778 /*{0x00001404} - DDR SDRAM Configuration Register */
779 reg = 0x3630B800;
785 /* {0x00001408} - DDR SDRAM Timing (Low) Register */
786 reg = 0x0;
788 /* tRAS - (0:3,20) */
792 0, 0xF, 16, 0x10);
795 reg |= (tmp & 0xF);
796 reg |= ((tmp & 0x10) << 16); /* to bit 20 */
801 4, 0xF, 0, 0);
804 reg |= ((tmp & 0xF) << 4);
809 8, 0xF, 0, 0);
812 reg |= ((tmp & 0xF) << 8);
817 12, 0xF, 0, 0);
820 reg |= ((tmp & 0xF) << 12);
825 16, 0xF, 0, 0);
828 reg |= ((tmp & 0xF) << 16);
833 24, 0xF, 0, 0);
836 reg |= ((tmp & 0xF) << 24);
841 28, 0xF, 0, 0);
844 reg |= ((tmp & 0xF) << 28);
847 reg = 0x33137663;
851 /*{0x0000140C} - DDR SDRAM Timing (High) Register */
853 reg = 0x39F8FF80;
855 /* tRFC - (0:6,16:18) */
858 0, 0x7F, 9, 0x380);
861 reg |= (tmp & 0x7F);
862 reg |= ((tmp & 0x380) << 9); /* to bit 16 */
865 /*{0x00001410} - DDR SDRAM Address Control Register */
866 reg = 0x000F0000;
871 spd_val = ddr3_div(tmp, ddr_clk_time, 0);
873 24, 0x3F, 0, 0);
876 reg |= ((tmp & 0x3F) << 24);
880 spd_val = ddr3_div(tmp, ddr_clk_time, 0);
882 24, 0x1F, 0, 0);
885 reg |= ((tmp & 0x1F) << 24);
890 reg |= (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) & 0xF0FFFF);
894 cs_count = 0;
895 dimm_cnt = 0;
896 for (cs = 0; cs < MAX_CS; cs++) {
900 cs_count = 0;
903 if (dimm_info[dimm_cnt].sdram_capacity < 0x3) {
907 } else if (dimm_info[dimm_cnt].sdram_capacity > 0x3) {
908 reg |= ((dimm_info[dimm_cnt].sdram_capacity & 0x3) <<
911 reg |= ((dimm_info[dimm_cnt].sdram_capacity & 0x4) <<
918 cs_count = 0;
919 dimm_cnt = 0;
920 for (cs = 0; cs < MAX_CS; cs++) {
924 cs_count = 0;
934 /*{0x00001418} - DDR SDRAM Operation Register */
935 reg = 0xF00;
936 for (cs = 0; cs < MAX_CS; cs++) {
942 /*{0x00001420} - DDR SDRAM Extended Mode Register */
943 reg = 0x00000004;
946 /*{0x00001424} - DDR Controller Control (High) Register */
948 reg = 0x0000D3FF;
950 reg = 0x0100D1FF;
954 /*{0x0000142C} - DDR3 Timing Register */
955 reg = 0x014C2F38;
957 reg = 0x1FEC2F38;
959 reg_write(0x142C, reg);
961 /*{0x00001484} - MBus CPU Block Register */
964 reg_write(REG_MBUS_CPU_BLOCK_ADDR, 0x0000E907);
971 /*{0x00001494} - DDR SDRAM ODT Control (Low) Register */
975 /*{0x00001498} - DDR SDRAM ODT Control (High) Register */
976 reg = 0x00000000;
979 /*{0x0000149C} - DDR Dunit ODT Control Register */
983 /*{0x000014A0} - DDR Dunit ODT Control Register */
985 reg = 0x000006A9;
989 /*{0x000014C0} - DRAM address and Control Driving Strenght */
990 reg_write(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR, 0x192435e9);
992 /*{0x000014C4} - DRAM Data and DQS Driving Strenght */
993 reg_write(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR, 0xB2C35E9);
996 /*{0x000014CC} - DRAM Main Pads Calibration Machine Control Register */
998 reg_write(REG_DRAM_MAIN_PADS_CAL_ADDR, reg | (1 << 0));
1003 /* 0x14CC[4:3] - CalUpdateControl = IntOnly */
1005 reg &= 0xFFFFFFE7;
1011 cs_count = 0;
1012 dimm_cnt = 0;
1013 for (cs = 0; cs < MAX_CS; cs++) {
1019 cs_count = 0;
1022 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8),
1025 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8), 0);
1031 /*{0x00020184} - Close FastPath - 2G */
1032 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, 0);
1034 /*{0x00001538} - Read Data Sample Delays Register */
1035 reg = 0;
1036 for (cs = 0; cs < MAX_CS; cs++) {
1045 /*{0x0000153C} - Read Data Ready Delay Register */
1046 reg = 0;
1047 for (cs = 0; cs < MAX_CS; cs++) {
1058 reg = 0x00000600;
1060 reg |= ((tmp & 0x1) << 2);
1061 reg |= ((tmp & 0xE) << 3); /* to bit 4 */
1062 for (cs = 0; cs < MAX_CS; cs++) {
1070 reg = 0x00000044 & REG_DDR3_MR1_ODT_MASK;
1072 reg = 0x00000046 & REG_DDR3_MR1_ODT_MASK;
1074 for (cs = 0; cs < MAX_CS; cs++) {
1111 for (cs = 0; cs < MAX_CS; cs++) {
1121 reg = 0x00000000;
1122 for (cs = 0; cs < MAX_CS; cs++) {
1129 /* {0x00001428} - DDR ODT Timing (Low) Register */
1130 reg = 0;
1131 reg |= (((cl - cwl + 1) & 0xF) << 4);
1132 reg |= (((cl - cwl + 6) & 0xF) << 8);
1133 reg |= ((((cl - cwl + 6) >> 4) & 0x1) << 21);
1134 reg |= (((cl - 1) & 0xF) << 12);
1135 reg |= (((cl + 6) & 0x1F) << 16);
1138 /* {0x0000147C} - DDR ODT Timing (High) Register */
1139 reg = 0x00000071;
1145 /*{0x000015E0} - DDR3 Rank Control Register */
1147 cs_count = 0;
1148 dimm_cnt = 0;
1149 for (cs = 0; cs < MAX_CS; cs++) {
1153 cs_count = 0;
1169 /*{0xD00015E4} - ZQDS Configuration Register */
1170 reg = 0x00203c18;
1173 /* {0x00015EC} - DDR PHY */
1175 reg = 0xF800AAA5;
1177 reg = 0xF800A225;
1179 reg = 0xDE000025;
1181 reg = 0xF800A225;
1199 reg |= 0x8;
1210 for (rc = 0; rc < SPD_RDIMM_RC_NUM; rc++) {
1214 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS));
1215 reg |= ((dimm_info[0].dimm_rc[rc] &
1221 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS);
1222 /* 0x1418 - SDRAM Operation Register */
1227 * register for 0x0
1252 return val / divider + (val % divider > 0 ? 1 : 0) - sub;
1265 if (dimm_num > 0) {
1288 if (dimm_num > 0) {