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/openbmc/linux/drivers/firmware/broadcom/
H A Dbcm47xx_sprom.c76 if (err < 0) \
78 err = kstrto ## type(strim(buf), 0, &var); \
104 if (err < 0) in NVRAM_READ_VAL()
106 err = kstrtou32(strim(buf), 0, &val); in NVRAM_READ_VAL()
112 *val_lo = (val & 0x0000FFFFU); in NVRAM_READ_VAL()
113 *val_hi = (val & 0xFFFF0000U) >> 16; in NVRAM_READ_VAL()
125 if (err < 0) in nvram_read_leddc()
127 err = kstrtou32(strim(buf), 0, &val); in nvram_read_leddc()
134 if (val == 0xffff || val == 0xffffffff) in nvram_read_leddc()
137 *leddc_on_time = val & 0xff; in nvram_read_leddc()
[all …]
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.h16 #define DRP 0x00
17 #define DTR0 0x01
18 #define DTR1 0x02
19 #define DTR2 0x03
20 #define DTR3 0x04
21 #define DTR4 0x05
22 #define DPMC0 0x06
23 #define DPMC1 0x07
24 #define DRFC 0x08
25 #define DSCH 0x09
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dstate.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_init.h88 U8 LUN[8]; /* 0Ch */
100 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
101 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
102 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
104 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
105 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
106 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
108 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
112 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
113 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
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/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-regs.h13 #define UMC_CPURST 0x00000700
14 #define UMC_IDSRST 0x0000070C
15 #define UMC_IXMRST 0x00000714
16 #define UMC_HDMRST 0x00000718
17 #define UMC_MDMRST 0x0000071C
18 #define UMC_HDDRST 0x00000720
19 #define UMC_MDDRST 0x00000724
20 #define UMC_SIORST 0x00000728
21 #define UMC_GIORST 0x0000072C
22 #define UMC_HD2RST 0x00000734
[all …]
/openbmc/linux/drivers/video/fbdev/geode/
H A Ddisplay_gx1.h21 #define CONFIG_CCR3 0xc3
22 # define CONFIG_CCR3_MAPEN 0x10
23 #define CONFIG_GCR 0xb8
27 #define MC_BANK_CFG 0x08
28 # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
29 # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
30 # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
32 #define MC_GBASE_ADD 0x14
33 # define MC_GADD_GBADD_MASK 0x000003ff
37 #define DC_PAL_ADDRESS 0x70
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/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl837d.h28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0…
29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0
30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
[all …]
H A Dcla0b5.h27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
[all …]
/openbmc/linux/arch/mips/include/asm/mach-rc32434/
H A Dddr.h49 #define DDR0_PHYS_ADDR 0x18018000
52 #define DDR_MASK 0xffff0000
58 #define RC32434_DDR0_ATA_MSK 0x000000E0
60 #define RC32434_DDR0_DBW_MSK 0x00000100
62 #define RC32434_DDR0_WR_MSK 0x00000600
64 #define RC32434_DDR0_PS_MSK 0x00001800
66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000
68 #define RC32434_DDR0_RFC_MSK 0x000f0000
70 #define RC32434_DDR0_RP_MSK 0x00300000
72 #define RC32434_DDR0_AP_MSK 0x00400000
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c19 #define FSL_SRDSCR0_OFFS 0x0
20 #define FSL_SRDSCR0_DPP_1V2 0x00008800
21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
24 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
25 #define FSL_SRDSCR1_OFFS 0x4
26 #define FSL_SRDSCR1_PLLBW 0x00000040
27 #define FSL_SRDSCR2_OFFS 0x8
28 #define FSL_SRDSCR2_VDD_1V2 0x00800000
[all …]
/openbmc/linux/drivers/scsi/mpi3mr/mpi/
H A Dmpi30_transport.h20 #define MPI3_VERSION_MINOR (0)
22 #define MPI3_VERSION_DEV (0)
23 #define MPI3_DEVHANDLE_INVALID (0xffff)
73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
77 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
78 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
79 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000)
81 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000)
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dreg_aic.h20 #define AR_SM_BASE 0xa200
21 #define AR_SM1_BASE 0xb200
22 #define AR_AGC_BASE 0x9e00
24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
H A Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h11 #define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
12 #define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
13 #define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
14 #define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
15 #define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
16 #define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
17 #define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
18 #define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
20 #define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
23 #define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dirq_txx9.c38 #define TXx9_IRCER_ICE 0x00000001
41 #define TXx9_IRCR_LOW 0x00000000
42 #define TXx9_IRCR_HIGH 0x00000001
43 #define TXx9_IRCR_DOWN 0x00000002
44 #define TXx9_IRCR_UP 0x00000003
45 #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
48 #define TXx9_IRSCR_EIClrE 0x00000100
49 #define TXx9_IRSCR_EIClr_MASK 0x0000000f
52 #define TXx9_IRCSR_IF 0x00010000
53 #define TXx9_IRCSR_ILV_MASK 0x00000700
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dcuboot-acadia.c23 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
25 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
27 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
31 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
32 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
33 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
34 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
36 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-vi.yaml15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_firmware_img.c7 0x0, };
10 0x800, 0x00000000,
11 0x804, 0x00000001,
12 0x808, 0x0000fc00,
13 0x80c, 0x0000001c,
14 0x810, 0x801010aa,
15 0x814, 0x008514d0,
16 0x818, 0x00000040,
17 0x81c, 0x00000000,
18 0x820, 0x00000004,
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dtable.c10 0x800, 0x00000000,
11 0x804, 0x00000001,
12 0x808, 0x0000fc00,
13 0x80c, 0x0000001c,
14 0x810, 0x801010aa,
15 0x814, 0x008514d0,
16 0x818, 0x00000040,
17 0x81c, 0x00000000,
18 0x820, 0x00000004,
19 0x824, 0x00690000,
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Decc.h12 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
13 #define ECC_ENABLE 0x00000000 /* ECC enable register */
14 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */
15 #define ECC_FADDR 0x00000010 /* ECC fault address register */
16 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
17 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
18 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
25 * 31 5 4 3 2 1 0
27 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
28 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
[all …]
/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]

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