16dacafeaSSujith Manoharan /* 26dacafeaSSujith Manoharan * Copyright (c) 2015 Qualcomm Atheros Inc. 36dacafeaSSujith Manoharan * 46dacafeaSSujith Manoharan * Permission to use, copy, modify, and/or distribute this software for any 56dacafeaSSujith Manoharan * purpose with or without fee is hereby granted, provided that the above 66dacafeaSSujith Manoharan * copyright notice and this permission notice appear in all copies. 76dacafeaSSujith Manoharan * 86dacafeaSSujith Manoharan * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 96dacafeaSSujith Manoharan * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 106dacafeaSSujith Manoharan * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 116dacafeaSSujith Manoharan * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 126dacafeaSSujith Manoharan * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 136dacafeaSSujith Manoharan * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 146dacafeaSSujith Manoharan * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 156dacafeaSSujith Manoharan */ 166dacafeaSSujith Manoharan 176dacafeaSSujith Manoharan #ifndef REG_AIC_H 186dacafeaSSujith Manoharan #define REG_AIC_H 196dacafeaSSujith Manoharan 206dacafeaSSujith Manoharan #define AR_SM_BASE 0xa200 216dacafeaSSujith Manoharan #define AR_SM1_BASE 0xb200 226dacafeaSSujith Manoharan #define AR_AGC_BASE 0x9e00 236dacafeaSSujith Manoharan 246dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) 256dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 266dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 276dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 286dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 296dacafeaSSujith Manoharan 306dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4) 316dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8) 326dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 336dacafeaSSujith Manoharan 346dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) 356dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) 366dacafeaSSujith Manoharan #define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) 376dacafeaSSujith Manoharan 386dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + 0x4c4) 396dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + 0x4c8) 406dacafeaSSujith Manoharan #define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) 416dacafeaSSujith Manoharan 426dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0) 436dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4) 446dacafeaSSujith Manoharan 456dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0) 466dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4) 476dacafeaSSujith Manoharan 486dacafeaSSujith Manoharan #define AR_PHY_BT_COEX_4 (AR_AGC_BASE + 0x60) 496dacafeaSSujith Manoharan #define AR_PHY_BT_COEX_5 (AR_AGC_BASE + 0x64) 506dacafeaSSujith Manoharan 516dacafeaSSujith Manoharan /* AIC fields */ 526dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_ENABLE 0x80000000 536dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_ENABLE_S 31 546dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000 556dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24 566dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000 576dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17 586dacafeaSSujith Manoharan #define AR_PHY_AIC_F_WLAN 0x0001FC00 596dacafeaSSujith Manoharan #define AR_PHY_AIC_F_WLAN_S 10 606dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200 616dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9 626dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ENABLE 0x00000100 636dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ENABLE_S 8 646dacafeaSSujith Manoharan #define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE 656dacafeaSSujith Manoharan #define AR_PHY_AIC_BTTX_PWR_THR_S 1 666dacafeaSSujith Manoharan #define AR_PHY_AIC_ENABLE 0x00000001 676dacafeaSSujith Manoharan #define AR_PHY_AIC_ENABLE_S 0 686dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_REF_DELAY 0x00F00000 696dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_REF_DELAY_S 20 706dacafeaSSujith Manoharan #define AR_PHY_AIC_BT_IDLE_CFG 0x00080000 716dacafeaSSujith Manoharan #define AR_PHY_AIC_BT_IDLE_CFG_S 19 726dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_COND 0x00060000 736dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_COND_S 17 746dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800 756dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11 766dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700 776dacafeaSSujith Manoharan #define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8 786dacafeaSSujith Manoharan #define AR_PHY_AIC_RSSI_MAX 0x000000F0 796dacafeaSSujith Manoharan #define AR_PHY_AIC_RSSI_MAX_S 4 806dacafeaSSujith Manoharan #define AR_PHY_AIC_RSSI_MIN 0x0000000F 816dacafeaSSujith Manoharan #define AR_PHY_AIC_RSSI_MIN_S 0 826dacafeaSSujith Manoharan #define AR_PHY_AIC_RADIO_DELAY 0x7F000000 836dacafeaSSujith Manoharan #define AR_PHY_AIC_RADIO_DELAY_S 24 846dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000 856dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20 866dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000 876dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15 886dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000 896dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13 906dacafeaSSujith Manoharan #define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00 916dacafeaSSujith Manoharan #define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10 926dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200 936dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9 946dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100 956dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8 966dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF 976dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0 986dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x07F00000 996dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 20 1006dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x000FE000 1016dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 13 1026dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PWR_EST_LONG 0x00001000 1036dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PWR_EST_LONG_S 12 1046dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00000C00 1056dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 10 1066dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PERF_THR 0x000003E0 1076dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_PERF_THR_S 5 1086dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018 1096dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3 1106dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006 1116dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1 1126dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001 1136dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0 1146dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_DONE 0x80000000 1156dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_DONE_S 31 1166dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_ACTIVE 0x40000000 1176dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_ACTIVE_S 30 1186dacafeaSSujith Manoharan #define AR_PHY_AIC_MEAS_COUNT 0x3F000000 1196dacafeaSSujith Manoharan #define AR_PHY_AIC_MEAS_COUNT_S 24 1206dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000 1216dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18 1226dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800 1236dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_HOP_COUNT_S 11 1246dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0 1256dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_VALID_COUNT_S 4 1266dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008 1276dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3 1286dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004 1296dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2 1306dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_DONE 0x00000002 1316dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_DONE_S 1 1326dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ACTIVE 0x00000001 1336dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ACTIVE_S 0 1346dacafeaSSujith Manoharan 1356dacafeaSSujith Manoharan #define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000 1366dacafeaSSujith Manoharan #define AR_PHY_AIC_MEAS_MAG_MIN_S 22 1376dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000 1386dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_STALE_COUNT_S 15 1396dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00 1406dacafeaSSujith Manoharan #define AR_PHY_AIC_MON_HOP_COUNT_S 8 1416dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_AIC_SM 0x000000F8 1426dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_AIC_SM_S 3 1436dacafeaSSujith Manoharan #define AR_PHY_AIC_SM 0x00000007 1446dacafeaSSujith Manoharan #define AR_PHY_AIC_SM_S 0 1456dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VALID 0x00000001 1466dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VALID_S 0 1476dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E 1486dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1 1496dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080 1506dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7 1516dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00 1526dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8 1536dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000 1546dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14 1556dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000 1566dacafeaSSujith Manoharan #define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15 1576dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x0000E000 1586dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 13 1596dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00001E00 1606dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 9 1616dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING 0x000001F8 1626dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S 3 1636dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF 0x00000006 1646dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S 1 1656dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000001 1666dacafeaSSujith Manoharan #define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 0 1676dacafeaSSujith Manoharan 1686dacafeaSSujith Manoharan #endif /* REG_AIC_H */ 169