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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
H A Dmcs_reg.h13 #define MCSX_IP_MODE 0x900c8ull
14 #define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({ \ argument
17 offset = 0x408ull; \
19 offset = 0xa28ull; \
20 offset += (a) * 0x8ull; \
24 #define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({ \ argument
27 offset = 0x808ull; \
29 offset = 0xa68ull; \
30 offset += (a) * 0x8ull; \
36 offset = 0x80000ull; \
[all …]
/openbmc/qemu/target/tricore/
H A Dcsfr.h.inc1 /* A(ll) access permitted
5 A|R|E(offset, register, feature introducing reg)
7 NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
9 A(0xfe00, PCXI, TRICORE_FEATURE_13)
10 A(0xfe08, PC, TRICORE_FEATURE_13)
11 A(0xfe14, SYSCON, TRICORE_FEATURE_13)
12 R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
13 R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
14 E(0xfe20, BIV, TRICORE_FEATURE_13)
15 E(0xfe24, BTV, TRICORE_FEATURE_13)
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) argument
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) argument
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) argument
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) argument
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) argument
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) argument
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) argument
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc-opcode.h13 #define __REG_R0 0
46 #define __REGA0_0 0
80 #define _R0 0
113 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115 #define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116 #define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
128 (((uintptr_t)(i) & 0x8000) >> 15))
133 #define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
[all …]
/openbmc/linux/drivers/crypto/cavium/cpt/
H A Dcpt_common.h16 #define CPT_81XX_PCI_PF_DEVICE_ID 0xa040
17 #define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
31 #define VF_STATE_DOWN 0
39 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36)) argument
40 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36)) argument
41 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36)) argument
42 #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36)) argument
43 #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36)) argument
44 #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36)) argument
45 #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36)) argument
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau88x0_a3d.c21 a3dsrc_SetTimeConsts(a3dsrc_t * a, short HrtfTrack, short ItdTrack, in a3dsrc_SetTimeConsts() argument
24 vortex_t *vortex = (vortex_t *) (a->vortex); in a3dsrc_SetTimeConsts()
26 a3d_addrA(a->slice, a->source, A3D_A_HrtfTrackTC), HrtfTrack); in a3dsrc_SetTimeConsts()
28 a3d_addrA(a->slice, a->source, A3D_A_ITDTrackTC), ItdTrack); in a3dsrc_SetTimeConsts()
30 a3d_addrA(a->slice, a->source, A3D_A_GainTrackTC), GTrack); in a3dsrc_SetTimeConsts()
32 a3d_addrA(a->slice, a->source, A3D_A_CoeffTrackTC), CTrack); in a3dsrc_SetTimeConsts()
35 #if 0
37 a3dsrc_GetTimeConsts(a3dsrc_t * a, short *HrtfTrack, short *ItdTrack,
47 a3dsrc_SetAtmosTarget(a3dsrc_t * a, short aa, short b, short c, short d, in a3dsrc_SetAtmosTarget() argument
50 vortex_t *vortex = (vortex_t *) (a->vortex); in a3dsrc_SetAtmosTarget()
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dmd5-asm.S49 lwbrx reg,0,rWP; /* load data */
61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
69 add a,a,rT0; /* 1: a = a + f */ \
72 add a,a,w0; /* 1: a = a + wk */ \
74 rotrwi a,a,p; /* 1: a = a rotl x */ \
75 add d,d,w1; /* 2: a = a + wk */ \
76 add a,a,b; /* 1: a = a + b */ \
77 and rT0,a,b; /* 2: f = b and c */ \
78 andc rT1,c,a; /* 2: f' = ~b and d */ \
80 add d,d,rT0; /* 2: a = a + f */ \
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D059.out35 [0]:
2049 wrote 512/512 bytes at offset 0
2058 cluster size: 0 bytes
2059 vm state offset: 0 bytes
2062 … use relative paths with VMDK descriptor file $QUORUM_FILE: Cannot generate a base directory for q…
2069 read 512/512 bytes at offset 0
2277 e100000000: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2278 e100000010: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2279 e100000020: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
2280 e100000030: 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a ................
[all …]
/openbmc/qemu/target/arm/tcg/
H A Diwmmxt_helper.c15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * You should have received a copy of the GNU Lesser General Public
30 #define SIMD8_SET(v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
31 #define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
33 #define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
40 #define NBIT8(x) ((x) & 0x80)
41 #define NBIT16(x) ((x) & 0x8000)
42 #define NBIT32(x) ((x) & 0x80000000)
43 #define NBIT64(x) ((x) & 0x8000000000000000ULL)
[all …]
/openbmc/linux/lib/
H A Dglobtest.c12 module_param(verbose, bool, 0);
24 /* Can't get string literals into a particular section, so... */ in test()
47 * pointed-to strings to be in a particular section.
49 * Anyway, a test consists of:
50 * 1. Expected glob_match result: '1' or '0'.
54 * The list of tests is terminated with a final '\0' instead of
55 * a glob_match result character.
59 "1" "a\0" "a\0"
60 "0" "a\0" "b\0"
61 "0" "a\0" "aa\0"
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
[all …]
H A Dcl507d.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dmarked.json3 "EventCode": "0x3515e",
5 …"BriefDescription": "Marked branch instruction completed with a target address less than current i…
9 "EventCode": "0x2013a",
15 "EventCode": "0x1016e",
21 "EventCode": "0x301e4",
27 "EventCode": "0x101e2",
33 "EventCode": "0x4d148",
35 …ified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip d…
39 "EventCode": "0x2d128",
41 …ified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip d…
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
23 } while (0)
29 } while (0)
31 static bool trans_fli_s(DisasContext *ctx, arg_fli_s *a)
37 /* Values below are NaN-boxed to avoid a gen_nanbox_s(). */
39 0xffffffffbf800000, /* -1.0 */
40 0xffffffff00800000, /* minimum positive normal */
41 0xffffffff37800000, /* 1.0 * 2^-16 */
42 0xffffffff38000000, /* 1.0 * 2^-15 */
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
16 asm volatile(str(COPY(0, %0, 0))";" in copy()
25 asm volatile(str(COPY(0, %0, 1))";" in copy_first()
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
42 asm volatile(str(PASTE(0, %1, 0, 0))";" in paste()
43 "mfcr %0;" in paste()
55 asm volatile(str(PASTE(0, %1, 1, 1))";" in paste_last()
56 "mfcr %0;" in paste_last()
64 #define PPC_INST_COPY __COPY(0, 0, 0)
65 #define PPC_INST_COPY_FIRST __COPY(0, 0, 1)
[all …]
/openbmc/ipmitool/src/plugins/lan/
H A Dmd5.c14 in a product, an acknowledgment in the product documentation would be
32 (section A.5) but excluding the rest of Appendix A. It does not include
57 #undef BYTE_ORDER /* 1 = big-endian, -1 = little-endian, 0 = unknown */
61 # define BYTE_ORDER 0
64 #define T_MASK ((md5_word_t)~0)
65 #define T1 /* 0xd76aa478 */ (T_MASK ^ 0x28955b87)
66 #define T2 /* 0xe8c7b756 */ (T_MASK ^ 0x173848a9)
67 #define T3 0x242070db
68 #define T4 /* 0xc1bdceee */ (T_MASK ^ 0x3e423111)
69 #define T5 /* 0xf57c0faf */ (T_MASK ^ 0x0a83f050)
[all …]
/openbmc/linux/drivers/scsi/esas2r/
H A Desas2r.h15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
38 * You should have received a copy of the GNU General Public License
115 #define ESAS2R_FWCOREDUMP_SZ 0x80000
117 #define ESAS2R_TARG_ID_INV 0xFFFF
120 #define ESAS2R_INT_DIS_MASK 0
134 /* macro to get the lowest nonzero bit of a value */
135 #define LOBIT(x) ((x) & (0 - (x)))
141 #define esas2r_read_register_dword(a, reg) \ argument
142 readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dmarked.json3 "EventCode": "0x3013E",
5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n…
8 "EventCode": "0x4F056",
10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …
13 "EventCode": "0x24158",
18 "EventCode": "0x1E046",
20 …BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another c…
23 "EventCode": "0x3C04A",
25 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load"
28 "EventCode": "0x2C01C",
[all …]
/openbmc/rest-dbus/resources/
H A Djquery.min.js2 …a,b){"object"==typeof module&&"object"==typeof module.exports?module.exports=a.document?b(a,!0):fu… argument
4 …0}function Q(a,b,d,e){if(m.acceptData(a)){var f,g,h=m.expando,i=a.nodeType,j=i?m.cache:a,k=i?a[h]:… argument
5 …a,b,c,d,e)}m.Tween=Za,Za.prototype={constructor:Za,init:function(a,b,c,d,e,f){this.elem=a,this.pro… argument
/openbmc/u-boot/lib/
H A Dsha1.c29 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
30 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
58 ctx->total[0] = 0; in sha1_starts()
59 ctx->total[1] = 0; in sha1_starts()
61 ctx->state[0] = 0x67452301; in sha1_starts()
62 ctx->state[1] = 0xEFCDAB89; in sha1_starts()
63 ctx->state[2] = 0x98BADCFE; in sha1_starts()
64 ctx->state[3] = 0x10325476; in sha1_starts()
65 ctx->state[4] = 0xC3D2E1F0; in sha1_starts()
70 unsigned long temp, W[16], A, B, C, D, E; in sha1_process() local
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-debug.h43 #define __IWL_ERR_DEV(d, mode, f, a...) \ argument
46 __iwl_err((d), mode, f, ## a); \
47 } while (0)
48 #define IWL_ERR_DEV(d, f, a...) \ argument
49 __IWL_ERR_DEV(d, IWL_ERR_MODE_REGULAR, f, ## a)
50 #define IWL_ERR(m, f, a...) \ argument
51 IWL_ERR_DEV((m)->dev, f, ## a)
52 #define IWL_ERR_LIMIT(m, f, a...) \ argument
53 __IWL_ERR_DEV((m)->dev, IWL_ERR_MODE_RATELIMIT, f, ## a)
54 #define IWL_WARN(m, f, a...) \ argument
[all …]
/openbmc/linux/crypto/
H A Dmd5.c27 0xd4, 0x1d, 0x8c, 0xd9, 0x8f, 0x00, 0xb2, 0x04,
28 0xe9, 0x80, 0x09, 0x98, 0xec, 0xf8, 0x42, 0x7e,
42 u32 a, b, c, d; in md5_transform() local
44 a = hash[0]; in md5_transform()
49 MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); in md5_transform()
50 MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); in md5_transform()
51 MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); in md5_transform()
52 MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); in md5_transform()
53 MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); in md5_transform()
54 MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); in md5_transform()
[all …]
/openbmc/linux/arch/sparc/crypto/
H A Dopcodes.h9 #define FPD_ENCODE(x) (((x) >> 5) | ((x) & ~(0x20)))
12 #define RS2(x) (FPD_ENCODE(x) << 0)
15 #define IMM5_0(x) ((x) << 0)
18 #define CRC32C(a,b,c) \ argument
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
22 .word 0x81b02800;
24 .word 0x81b02820;
26 .word 0x81b02840;
28 .word 0x81b02860;
30 #define AES_EROUND01(a,b,c,d) \ argument
[all …]

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