| /openbmc/linux/drivers/media/platform/nxp/ |
| H A D | imx-pxp.h | 13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | imx-regs.h | 11 #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
12 #define IRAM_SIZE 0x00080000 /* 512 KB */
14 #define AIPS0_BASE_ADDR 0x40000000
15 #define AIPS1_BASE_ADDR 0x40080000
17 /* AIPS 0 */
18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx5/ |
| H A D | crm_regs.h | 29 u32 ccr; /* 0x0000 */
33 u32 cacrr; /* 0x0010*/
37 u32 cscmr2; /* 0x0020 */
41 u32 cdcdr; /* 0x0030 */
45 u32 cscdr4; /* 0x0040 */
49 u32 ctor; /* 0x0050 */
53 u32 ccosr; /* 0x0060 */
57 u32 CCGR2; /* 0x0070 */
61 u32 CCGR6; /* 0x0080 */
63 u32 CCGR7; /* 0x0084 */
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| /openbmc/linux/sound/soc/qcom/ |
| H A D | lpass-lpaif-reg.h | 11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
16 #define LPAIF_I2SCTL_LOOPBACK_DISABLE 0
19 #define LPAIF_I2SCTL_SPKEN_DISABLE 0
22 #define LPAIF_I2SCTL_MODE_NONE 0
45 #define LPAIF_I2SCTL_SPKMONO_STEREO 0
48 #define LPAIF_I2SCTL_MICEN_DISABLE 0
53 #define LPAIF_I2SCTL_MICMONO_STEREO 0
56 #define LPAIF_I2SCTL_WSSRC_INTERNAL 0
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 62 #define BPP_INVALID 0
63 #define BPP_BLENDED_PIPE 0xffffffff
397 struct vba_vars_st *v,
716 s = 0; in dscceComputeDelay()
728 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
731 lstall = 0; in dscceComputeDelay()
741 unsigned int Delay = 0; in dscComputeDelay()
747 Delay = Delay + 0; in dscComputeDelay()
791 Delay = Delay + 0; in dscComputeDelay()
1855 struct vba_vars_st *v = &mode_lib->vba; DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
3543 struct vba_vars_st *v = &mode_lib->vba; dml30_ModeSupportAndSystemConfigurationFull() local
6497 UseMinimumDCFCLK(struct display_mode_lib * mode_lib,struct vba_vars_st * v,int MaxPrefetchMode,int ReorderingBytes) UseMinimumDCFCLK() argument
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| /openbmc/linux/drivers/staging/media/sunxi/sun6i-isp/ |
| H A D | sun6i_isp_reg.h | 16 #define SUN6I_ISP_SRC_MODE_DRAM 0
19 #define SUN6I_ISP_FE_CFG_REG 0x0
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
24 #define SUN6I_ISP_FE_CTRL_REG 0x4
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
36 #define SUN6I_ISP_FE_INT_EN_REG 0x8
37 #define SUN6I_ISP_FE_INT_EN_FINISH BIT(0)
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| /openbmc/linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_h264_dec.c | 28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
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| H A D | rockchip_vpu2_hw_mpeg2_dec.c | 23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
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| H A D | hantro_g1_mpeg2_dec.c | 25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 27 #define UNIT_TEST 0
44 #define BPP_INVALID 0
45 #define BPP_BLENDED_PIPE 0xffffffff
89 #define BPP_INVALID 0
90 #define BPP_BLENDED_PIPE 0xffffffff
711 …unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay,… in dscceComputeDelay()
739 s = 0; in dscceComputeDelay()
751 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
754 lstall = 0; in dscceComputeDelay()
764 unsigned int Delay = 0; in dscComputeDelay()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 41 #define BPP_INVALID 0
42 #define BPP_BLENDED_PIPE 0xffffffff
88 #define BPP_INVALID 0
89 #define BPP_BLENDED_PIPE 0xffffffff
690 …unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay,… in dscceComputeDelay()
718 s = 0; in dscceComputeDelay()
730 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
733 lstall = 0; in dscceComputeDelay()
743 unsigned int Delay = 0; in dscComputeDelay()
749 Delay = Delay + 0; in dscComputeDelay()
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| /openbmc/linux/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-kirkwood.c | 19 #define V(f6180, f6190, f6192, f6281, f6282, dx4122, dx1135) \ macro
20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
35 MPP_MODE(0,
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| /openbmc/qemu/tests/tcg/xtensa/ |
| H A D | test_shift.S | 5 .macro test_shift prefix, dst, src, v, imm
6 \prefix\()_set \dst, \src, \v, \imm
7 \prefix\()_ver \dst, \v, \imm
10 .macro test_shift_sd prefix, v, imm
11 test_shift \prefix, a3, a2, \v, \imm
12 test_shift \prefix, a2, a2, \v, \imm
15 .macro tests_imm_shift prefix, v argument
16 test_shift_sd \prefix, \v, 1
17 test_shift_sd \prefix, \v, 2
18 test_shift_sd \prefix, \v, 7
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| /openbmc/linux/tools/testing/selftests/bpf/progs/ |
| H A D | map_kptr_fail.c | 27 struct map_value *v; in size_not_bpf_dw() local
28 int key = 0; in size_not_bpf_dw()
30 v = bpf_map_lookup_elem(&array_map, &key); in size_not_bpf_dw()
31 if (!v) in size_not_bpf_dw()
32 return 0; in size_not_bpf_dw()
34 *(u32 *)&v->unref_ptr = 0; in size_not_bpf_dw()
35 return 0; in size_not_bpf_dw()
42 struct map_value *v; in non_const_var_off() local
43 int key = 0, id; in non_const_var_off()
45 v = bpf_map_lookup_elem(&array_map, &key); in non_const_var_off()
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| /openbmc/linux/drivers/iommu/ |
| H A D | msm_iommu_hw-8xxx.h | 20 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
28 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
29 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
30 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
31 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
35 #define SET_FIELD(addr, mask, shift, v) \ argument
38 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
39 } while (0)
47 #define FL_BASE_MASK 0xFFFFFC00
48 #define FL_TYPE_TABLE (1 << 0)
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | x86.csv | 58 # but only 4bits are meaningful while the others are ignored or must be 0.
105 # V, I, N.E., N.P., N.S., or N.I.
107 # column is "V" (valid) or not.
110 # with an incorrect "V" in the Valid32 column.
142 # Using refining prefix like 0x66 will lead to 32-bit operation (if supported).
176 "PUSH imm32","-/PUSHL/PUSHQ imm32","-/pushl/pushq imm32","68 id","V","N.S.","","operand32","r","Y",…
177 "PUSH imm32","-/PUSHL/PUSHQ imm32","-/pushl/pushq imm32","68 id","N.S.","V","","default64","r","Y",…
178 "AAA","AAA","aaa","37","V","N.S.","","","","",""
179 "AAD","AAD","aad","D5 0A","V","I","","pseudo","","",""
180 "AAD imm8u","AAD imm8u","aad imm8u","D5 ib","V","N.S.","","","r","",""
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| /openbmc/linux/drivers/gpu/host1x/hw/ |
| H A D | hw_host1x01_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x06_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x04_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x07_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x08_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x05_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| H A D | hw_host1x02_uclass.h | 15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | stm32-dfsdm.h | 19 * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
21 * | 0x020 | CHANNEL 1 |
25 * | 0x20 x n | CHANNEL n |
27 * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
29 * | 0x200 | FILTER 1 |
33 * | 0x100 x m | FILTER m |
37 * | 0x7F0-7FC | Identification registers |
44 #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
45 #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
46 #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | vgic_init.c | 23 #define GICR_TYPER 0x8
57 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get()
63 GUEST_SYNC(0); in guest_code()
72 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu()
79 struct vm_gic v; in vm_gic_create_with_vcpus() local
81 v.gic_dev_type = gic_dev_type; in vm_gic_create_with_vcpus()
82 v.vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); in vm_gic_create_with_vcpus()
83 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_with_vcpus()
85 return v; in vm_gic_create_with_vcpus()
90 struct vm_gic v; in vm_gic_create_barebones() local
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