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/openbmc/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
16 #include <linux/mfd/syscon/xlnx-vcu.h>
22 #include <dt-bindings/clock/xlnx-vcu.h>
24 #define VCU_PLL_CTRL 0x24
25 #define VCU_PLL_CTRL_RESET BIT(0)
32 #define VCU_PLL_CFG 0x28
33 #define VCU_PLL_CFG_RES GENMASK(3, 0)
38 #define VCU_ENC_CORE_CTRL 0x30
[all …]
/openbmc/linux/drivers/misc/cxl/
H A Dcxl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #include <misc/cxl-base.h>
64 /* Configuration and Control area - CAIA 1&2 */
65 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
66 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
67 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
68 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
69 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
71 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
72 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
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/openbmc/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
44 # NI - Not implemented
45 # IMP - Implemented
51 Sysreg OSDTRRX_EL1 2 0 0 0 2
52 Res0 63:32
53 Field 31:0 DTRRX
56 Sysreg MDCCINT_EL1 2 0 0 2 0
57 Res0 63:31
60 Res0 28:0
63 Sysreg MDSCR_EL1 2 0 0 2 2
[all …]
/openbmc/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
17 #define IRDMA_IRD_HW_SIZE_4 0
24 IRDMA_ANY_PROTOCOL = 0,
29 #define IRDMA_QP_STATE_INVALID 0
55 #define RDMA_OPCODE_M 0x0f
58 #define CQE_MAJOR_DRV 0x8000
69 #define IRDMA_AE_SOURCE_RSVD 0x0
70 #define IRDMA_AE_SOURCE_RQ 0x1
71 #define IRDMA_AE_SOURCE_RQ_0011 0x3
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H A Duda_d.h1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
7 #define IRDMA_E_UDA_SQ_L4T_UNKNOWN 0
13 #define IRDMA_E_UDA_SQ_IIPT_UNKNOWN 0
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
43 /* Byte Offset 0 */
73 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0)
74 #define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0)
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dctl_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define CR0_CLOCK_COMPARATOR_SIGN BIT(63 - 10)
14 #define CR0_LOW_ADDRESS_PROTECTION BIT(63 - 35)
15 #define CR0_FETCH_PROTECTION_OVERRIDE BIT(63 - 38)
16 #define CR0_STORAGE_PROTECTION_OVERRIDE BIT(63 - 39)
17 #define CR0_EMERGENCY_SIGNAL_SUBMASK BIT(63 - 49)
18 #define CR0_EXTERNAL_CALL_SUBMASK BIT(63 - 50)
19 #define CR0_CLOCK_COMPARATOR_SUBMASK BIT(63 - 52)
20 #define CR0_CPU_TIMER_SUBMASK BIT(63 - 53)
21 #define CR0_SERVICE_SIGNAL_SUBMASK BIT(63 - 54)
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H A Dirq.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define EXT_INTERRUPT 0
15 #define EXT_IRQ_INTERRUPT_KEY 0x0040
16 #define EXT_IRQ_CLK_COMP 0x1004
17 #define EXT_IRQ_CPU_TIMER 0x1005
18 #define EXT_IRQ_WARNING_TRACK 0x1007
19 #define EXT_IRQ_MALFUNC_ALERT 0x1200
20 #define EXT_IRQ_EMERGENCY_SIG 0x1201
21 #define EXT_IRQ_EXTERNAL_CALL 0x1202
22 #define EXT_IRQ_TIMING_ALERT 0x1406
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H A Dnmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define MCIC_SUBCLASS_MASK (1ULL<<63 | 1ULL<<62 | 1ULL<<61 | \
22 #define MCCK_CODE_SYSTEM_DAMAGE BIT(63)
23 #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5)
24 #define MCCK_CODE_CP BIT(63 - 9)
25 #define MCCK_CODE_STG_ERROR BIT(63 - 16)
26 #define MCCK_CODE_STG_KEY_ERROR BIT(63 - 18)
27 #define MCCK_CODE_STG_DEGRAD BIT(63 - 19)
28 #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20)
29 #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23)
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/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_masking.c1 // SPDX-License-Identifier: GPL-2.0
10 __success __success_unpriv __retval(0)
16 r2 -= r1; \ in test_out_of_bounds_1()
18 r2 = -r2; \ in test_out_of_bounds_1()
19 r2 s>>= 63; \ in test_out_of_bounds_1()
24 : __imm_const(__imm_0, 5 - 1) in test_out_of_bounds_1()
30 __success __success_unpriv __retval(0)
36 r2 -= r1; \ in test_out_of_bounds_2()
38 r2 = -r2; \ in test_out_of_bounds_2()
39 r2 s>>= 63; \ in test_out_of_bounds_2()
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/openbmc/qemu/tests/qemu-iotests/tests/
H A Dqcow2-internal-snapshots.out1 QA output created by qcow2-internal-snapshots
6 QEMU X.Y.Z monitor - type 'help' for more information
7 (qemu) qemu-io disk0 "write -P0x11 0 1M"
8 wrote 1048576/1048576 bytes at offset 0
11 (qemu) qemu-io disk0 "write -P0x22 0 512k"
12 wrote 524288/524288 bytes at offset 0
18 1 snap0 SIZE yyyy-mm-dd hh:mm:ss 0000:00:00.000 --
23 QEMU X.Y.Z monitor - type 'help' for more information
24 (qemu) qemu-io disk0 "read -P0x11 0 1M"
25 read 1048576/1048576 bytes at offset 0
[all …]
H A Dqcow2-internal-snapshots25 seq="$(basename $0)"
34 trap "_cleanup; exit \$status" 0 1 2 3 15
40 # This tests qcow2-specific low-level functionality
45 _unsupported_imgopts 'compat=0.10' 'refcount_bits=1[^0-9]' data_file
51 $QEMU -no-shutdown -nographic -monitor stdio -serial none \
52 -blockdev file,filename="$TEST_IMG",node-name=disk0-file \
53 -blockdev "$IMGFMT",file=disk0-file,node-name=disk0 \
54 -object iothread,id=iothread0 \
55 -device virtio-scsi,iothread=iothread0 \
56 -device scsi-hd,drive=disk0,share-rw=on \
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/openbmc/linux/Documentation/sound/cards/
H A Daudigy-mixer.rst5 This is based on sb-live-mixer.rst.
20 functionality. Only the default built-in code in the ALSA driver is described
34 one-way three wire serial bus for digital sound by Philips Semiconductors
42 FX-bus
47 name='PCM Front Playback Volume',index=0
48 ----------------------------------------
49 This control is used to attenuate samples from left and right front PCM FX-bus
53 name='PCM Surround Playback Volume',index=0
54 -------------------------------------------
55 This control is used to attenuate samples from left and right surround PCM FX-bus
[all …]
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/starfive-jh7100.h>
18 #include "clk-starfive-jh71x0.h"
21 #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
59 JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
76 JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
77 JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
78 JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
93 JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dhvcall.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #define HVSC .long 0x44000022
8 #define H_SUCCESS 0
9 #define H_BUSY 1 /* Hardware busy -- retry later */
37 #define H_HARDWARE -1 /* Hardware error */
38 #define H_FUNCTION -2 /* Function not supported */
39 #define H_PRIVILEGE -3 /* Caller not privileged */
40 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
41 #define H_BAD_MODE -5 /* Illegal msr value */
42 #define H_PTEG_FULL -6 /* PTEG is full */
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_npc_hash.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define RVU_NPC_HASH_SECRET_KEY0 0xa9d5af4c9fbc76b1
12 #define RVU_NPC_HASH_SECRET_KEY1 0xa9d5af4c9fbc87b4
13 #define RVU_NPC_HASH_SECRET_KEY2 0x5954c9e7
20 ((ena) << 7) | ((flags_ena) << 6) | ((key_ofs) & 0x3F))
24 ((ltype_match) << 4) | ((ltype_mask) & 0xF))
45 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
47 /* NPC_AF_INTF(0..1)_HASH(0..1)_CFG */
49 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
51 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dsev-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define GHCB_MSR_INFO_POS 0
13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
19 #define GHCB_MSR_SEV_INFO_RESP 0x001
20 #define GHCB_MSR_SEV_INFO_REQ 0x002
23 /* GHCBData[63:48] */ \
24 ((((_max) & 0xffff) << 48) | \
26 (((_min) & 0xffff) << 32) | \
28 (((_cbit) & 0xff) << 24) | \
31 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
[all …]
/openbmc/linux/drivers/crypto/cavium/cpt/
H A Dcpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 CPT_COMP_E_NOTDONE = 0x00,
19 CPT_COMP_E_GOOD = 0x01,
20 CPT_COMP_E_FAULT = 0x02,
21 CPT_COMP_E_SWERR = 0x03,
22 CPT_COMP_E_LAST_ENTRY = 0xFF
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
32 * Word 0
34 * 0 = No interrupts related to this instruction.
42 * Address must be 16-byte aligned.
[all …]
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 3 2 1 0
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/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_RF.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
24 pDM_Odm->CutVersion << 24 | in CheckPositive()
25 pDM_Odm->SupportPlatform << 16 | in CheckPositive()
26 pDM_Odm->PackageType << 12 | in CheckPositive()
[all …]
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
10 * https://github.com/riscv-non-isa/riscv-iommu
16 #define RISCV_IOMMU_SPEC_DOT_VER 0x010
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
33 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0)
[all …]
/openbmc/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 while (((1U << ld) - 1) < queue_entries) in get_order_of_qentries()
25 return ld - 1; in get_order_of_qentries()
47 for (i = 0; i < 5; i++) { in ehea_plpar_hcall_norets()
86 for (i = 0; i < 5; i++) { in ehea_plpar_hcall9()
114 outs[0], outs[1], outs[2], outs[3], outs[4], in ehea_plpar_hcall9()
131 0, 0); in ehea_h_query_ehea_qp()
144 #define H_ALL_RES_QP_RES_TYP EHEA_BMASK_IBM(56, 63)
147 #define H_ALL_RES_QP_TOKEN EHEA_BMASK_IBM(0, 31)
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/openbmc/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0
17 #define OTX_CPT_PCI_PF_DEVICE_ID 0xa040
18 #define OTX_CPT_PCI_VF_DEVICE_ID 0xa041
20 #define OTX_CPT_PCI_PF_SUBSYS_ID 0xa340
21 #define OTX_CPT_PCI_VF_SUBSYS_ID 0xa341
24 #define OTX_CPT_PF_PCI_CFG_BAR 0
25 #define OTX_CPT_VF_PCI_CFG_BAR 0
28 (0x000020000000ll + 0x1000000000ll * (a) + 0x100000ll * (b))
29 #define OTX_CPT_BAR_E_CPTX_VFX_BAR0_SIZE 0x400000
46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcavium-pip.txt10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
32 - compatible: "cavium,octeon-3860-pip-port"
36 - reg: The port number within the interface group.
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h4 * Copyright (c) 2013-2020, IBM Corporation.
7 * COPYING file in the top-level directory.
13 #include "qemu/host-utils.h"
19 #define PBCQ_NEST_IRSN_COMPARE 0x1a
20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
21 #define PBCQ_NEST_IRSN_MASK 0x1b
22 #define PBCQ_NEST_LSI_SRC_ID 0x1f
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
24 #define PBCQ_NEST_REGS_COUNT 0x46
25 #define PBCQ_NEST_MMIO_BAR0 0x40
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/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dciu2.txt4 - compatible: "cavium,octeon-6880-ciu2"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is the bank within
13 the CIU and may have a value between 0 and 63. The second cell is
14 the bit within the bank and may also have a value between 0 and 63.
17 interrupt-controller@1070100000000 {
18 compatible = "cavium,octeon-6880-ciu2";
19 interrupt-controller;
21 * 1) Controller register (0..63)
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