| /openbmc/qemu/include/libdecnumber/ |
| H A D | decDPD.h | 29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
45 /* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
[all …]
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | tie.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Copyright (C) 1999-2015 Cadence Design Systems Inc.
14 #define XCHAL_CP_NUM 0 /* number of coprocessors */
15 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
16 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
17 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
19 /* Save area for non-coprocessor optional and custom (TIE) state: */
24 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
37 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
38 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
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| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
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| /openbmc/linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 0 /* number of coprocessors */
36 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
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| /openbmc/linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
43 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
48 #define XCHAL_CP0_SA_SIZE 0
50 #define XCHAL_CP1_SA_SIZE 0
52 #define XCHAL_CP2_SA_SIZE 0
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| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 23 * If page size and eraseblock size are 0, the sizes are taken from the
28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
43 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | get-reg-list.c | 1 // SPDX-License-Identifier: GPL-2.0
27 ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */
28 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
29 0,
33 ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */
34 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
39 ARM64_SYS_REG(3, 0, 10, 2, 3), /* PIR_EL1 */
40 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
63 for (i = 0; i < ARRAY_SIZE(feat_id_regs); i++) { in check_supported_feat_reg()
66 if (ret < 0) in check_supported_feat_reg()
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| /openbmc/linux/drivers/staging/vt6655/ |
| H A D | rf.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 * IFRFbWriteEmbedded - Embedded write RF register via MAC
37 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
38 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
39 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
40 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
41 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
42 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
43 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
44 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
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| H A D | sm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
16 return -ERANGE; in oob_sm_ooblayout_ecc()
18 oobregion->length = 3; in oob_sm_ooblayout_ecc()
19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()
21 return 0; in oob_sm_ooblayout_ecc()
28 case 0: in oob_sm_ooblayout_free()
30 oobregion->offset = 0; in oob_sm_ooblayout_free()
31 oobregion->length = 4; in oob_sm_ooblayout_free()
35 oobregion->offset = 6; in oob_sm_ooblayout_free()
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| /openbmc/linux/arch/mips/boot/dts/cavium-octeon/ |
| H A D | octeon_68xx.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
16 soc@0 {
17 compatible = "simple-bus";
18 #address-cells = <2>;
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| H A D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
6 * use. Because of this, it contains a super-set of the available
13 soc@0 {
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
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| /openbmc/linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
33 #define RK3228_PDATAEN_DISABLE BIT(0)
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| /openbmc/linux/fs/exfat/ |
| H A D | balloc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2013 Samsung Electronics Co., Ltd.
14 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2,/* 0 ~ 19*/
15 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2, 0, 1, 0, 3,/* 20 ~ 39*/
16 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2,/* 40 ~ 59*/
17 0, 1, 0, 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4,/* 60 ~ 79*/
18 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5, 0, 1, 0, 2,/* 80 ~ 99*/
19 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3,/*100 ~ 119*/
20 0, 1, 0, 2, 0, 1, 0, 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2,/*120 ~ 139*/
21 0, 1, 0, 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, 5,/*140 ~ 159*/
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
29 #define Op0_mask 0x3
31 #define Op1_mask 0x7
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| /openbmc/u-boot/lib/libavb/ |
| H A D | avb_sha256.c | 1 // SPDX-License-Identifier: BSD-3-Clause
6 * FIPS 180-2 SHA-224/256/384/512 implementation
14 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
15 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
21 #define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
26 *((str) + 3) = (uint8_t)((x)); \
29 *((str) + 0) = (uint8_t)((x) >> 24); \
34 *(x) = ((uint32_t) * ((str) + 3)) | ((uint32_t) * ((str) + 2) << 8) | \
36 ((uint32_t) * ((str) + 0) << 24); \
42 { w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + w[i - 16]; }
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| /openbmc/linux/tools/testing/selftests/cgroup/ |
| H A D | test_cpuset_prs.sh | 2 # SPDX-License-Identifier: GPL-2.0
16 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"
20 WAIT_INOTIFY=$(cd $(dirname $0); pwd)/wait_inotify
23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"
26 CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
27 [[ $CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"
34 while [[ "$1" = -* ]]
37 -v) VERBOSE=1
39 [[ $DELAY_FACTOR -eq 1 ]] &&
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| /openbmc/linux/tools/arch/arm64/include/asm/ |
| H A D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
26 #define Op0_mask 0x3
28 #define Op1_mask 0x7
30 #define CRn_mask 0xf
32 #define CRm_mask 0xf
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| /openbmc/linux/arch/powerpc/boot/dts/ |
| H A D | mucmc52.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
74 phy-handle = <&phy0>;
[all …]
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| H A D | charon.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpc5200_pic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
28 d-cache-line-size = <32>;
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| /openbmc/linux/Documentation/input/devices/ |
| H A D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
17 3. Differentiating hardware versions
25 5.2.1 Parity checking and packet re-synchronization
27 5.2.3 Two finger touch
28 6. Hardware version 3
38 7.2.3 Motion packet
39 8. Trackpoint (for Hardware version 3 and 4)
50 hardware versions unimaginatively called version 1,version 2, version 3
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
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| /openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
| H A D | regs-digctl.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <asm/mach-imx/regs-common.h>
15 mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
16 mxs_reg_32(hw_digctl_status) /* 0x010 */
17 mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
18 mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
19 mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
20 mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
21 uint32_t hw_digctl_writeonce; /* 0x060 */
22 uint32_t reserved_writeonce[3];
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | grf_rk3128.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 unsigned int reserved[0x2a];
31 unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
69 unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
73 unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
77 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
96 check_member(rk3128_pmu, int_st, 0x34);
101 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
102 GPIO0A7_GPIO = 0,
106 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
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