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/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
H A Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
/openbmc/linux/drivers/misc/
H A Dsram.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Generic on-chip SRAM allocation driver
19 #include <soc/at91/atmel-secumod.h>
21 #include "sram.h"
33 mutex_lock(&part->lock); in sram_read()
34 memcpy_fromio(buf, part->base + pos, count); in sram_read()
35 mutex_unlock(&part->lock); in sram_read()
48 mutex_lock(&part->lock); in sram_write()
49 memcpy_toio(part->base + pos, buf, count); in sram_write()
50 mutex_unlock(&part->lock); in sram_write()
[all …]
H A Dsram-exec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SRAM protect-exec region helper functions
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/sram.h>
17 #include "sram.h"
22 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
25 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec()
26 unsigned long end = base + block->size; in sram_check_protect_exec()
29 dev_err(sram->dev, in sram_check_protect_exec()
30 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dsram-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP SRAM detection and management
22 #include "sram.h"
26 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
35 * Memory allocator for SRAM: calculates the new ceiling address
39 * to an 8-byte boundary.
45 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
48 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
52 new_ceil -= size; in omap_sram_push_address()
61 void *sram; in omap_sram_push() local
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsram.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * OMAP SRAM detection and management
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
29 #include "sram.h"
48 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
57 * Memory allocator for SRAM: calculates the new ceiling address
61 * to an 8-byte boundary.
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
70 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
H A Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
[all …]
/openbmc/u-boot/board/samsung/common/
H A Dexynos-uboot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
11 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
14 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
26 } >.sram
29 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
32 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
37 } >.sram
40 .machine_param : { *(.machine_param) } >.sram
48 } >.sram
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dsram.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * mach/sram.h - DaVinci simple SRAM allocator
10 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14 * SRAM allocations return a CPU virtual address, or NULL on error.
15 * If a DMA address is requested and the SRAM supports DMA, its
18 * Errors include SRAM memory not being available, and requesting
19 * DMA mapped SRAM on systems which don't allow that.
/openbmc/linux/drivers/mtd/devices/
H A Dms02-nv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for
16 * 0x000000 - 0x3fffff SRAM
17 * 0x400000 - 0x7fffff CSR
19 * Within the SRAM area the following ranges are forced by the system
22 * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot
23 * 0x000400 - ENDofRAM storage area, available to operating systems
28 * ID value is found, the firmware considers the SRAM clean, i.e.
31 * for the start address of the user-available is 0x001000 which is
36 * operating system, a magic ID to distinguish a MS02-NV board from
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dmv_cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 - reg: base physical address of the engine and length of memory mapped
9 region. Can also contain an entry for the SRAM attached to the CESA,
10 but this representation is deprecated and marvell,crypto-srams should
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
13 is deprecated and marvell,crypto-srams should be used instead
14 - interrupts: interrupt number
[all …]
H A Dmarvell-cesa.txt4 - compatible: should be one of the following string
5 "marvell,orion-crypto"
6 "marvell,kirkwood-crypto"
7 "marvell,dove-crypto"
8 "marvell,armada-370-crypto"
9 "marvell,armada-xp-crypto"
10 "marvell,armada-375-crypto"
11 "marvell,armada-38x-crypto"
12 - reg: base physical address of the engine and length of memory mapped
13 region. Can also contain an entry for the SRAM attached to the CESA,
[all …]
/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
29 the system SRAM) for different peripheral. It can access external RAMs but
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
[all …]
/openbmc/u-boot/board/Barix/ipam390/
H A Du-boot-spl-ipam390.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
10 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
13 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
27 } >.sram
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
40 } >.sram
49 } >.sram
56 } >.sram
/openbmc/u-boot/board/davinci/da8xxevm/
H A Du-boot-spl-da850evm.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
10 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
13 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
27 } >.sram
30 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
33 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
36 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
43 } >.sram
52 } >.sram
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c18 #include "hw-ops.h"
42 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; in ar9003_hw_is_aic_enabled()
46 * HW code and the driver-layer support ready. in ar9003_hw_is_aic_enabled()
50 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_AIC) in ar9003_hw_is_aic_enabled()
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
74 i = -1; in ar9003_aic_find_valid()
84 int16_t i = -1; in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
94 i--; in ar9003_aic_find_index()
100 i = -1; in ar9003_aic_find_index()
[all …]
/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pm.c1 // SPDX-License-Identifier: GPL-2.0
12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
24 static void __iomem *sram; variable
44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
50 tmp = in_be16(&gpiow->wkup_itype); in mpc52xx_set_wakeup_gpio()
53 out_be16(&gpiow->wkup_itype, tmp); in mpc52xx_set_wakeup_gpio()
55 out_8(&gpiow->wkup_maste, 1); in mpc52xx_set_wakeup_gpio()
64 { .compatible = "fsl,mpc5200-immr", }, in mpc52xx_pm_prepare()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
14 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,
19 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
29 } >.sram
34 } >.sram
39 } >.sram
44 } >.sram
49 } >.sram
54 } >.sram
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dcanaan,k210-sram.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
15 - Conor Dooley <conor@kernel.org>
20 - canaan,k210-sram
25 - description: sram0 clock
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-orion-net.txt12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
30 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
35 - compatible: shall be one of "marvell,orion-eth-port",
36 "marvell,kirkwood-eth-port".
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Damlogic,meson-mx-ao-arc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 controller for always-on operations, typically used for managing
17 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
22 - enum:
23 - amlogic,meson8-ao-arc
24 - amlogic,meson8b-ao-arc
25 - const: amlogic,meson-mx-ao-arc
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * January 2004 - Changed to support H4 device
9 * Copyright (c) 2004-2008 Texas Instruments
15 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
18 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
29 } > .sram
32 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
35 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
40 } > .sram
53 } > .sram
/openbmc/linux/drivers/memory/
H A Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Du-boot-spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
7 MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE, \
12 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
23 } >.sram
26 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
29 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
32 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
40 } >.sram
53 ASSERT(__image_copy_end - __start < (IMAGE_MAX_SIZE), \
58 ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \

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