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/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/fonts/
H A Dfontawesome-webfont.svg2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd" >
6 <font id="fontawesomeregular" horiz-adv-x="1536" >
7 <font-face units-per-em="1792" ascent="1536" descent="-256" />
8 <missing-glyph horiz-adv-x="448" />
9 <glyph unicode=" " horiz-adv-x="448" />
10 <glyph unicode="&#x09;" horiz-adv-x="448" />
11 <glyph unicode="&#xa0;" horiz-adv-x="448" />
12 <glyph unicode="&#xa8;" horiz-adv-x="1792" />
13 <glyph unicode="&#xa9;" horiz-adv-x="1792" />
14 <glyph unicode="&#xae;" horiz-adv-x="1792" />
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H A Dglyphicons-halflings-regular.svg2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd" >
6 <font id="glyphicons_halflingsregular" horiz-adv-x="1200" >
7 <font-face units-per-em="1200" ascent="960" descent="-240" />
8 <missing-glyph horiz-adv-x="500" />
9 <glyph horiz-adv-x="0" />
10 <glyph horiz-adv-x="400" />
12 …-1.5t30 -3.5l11 -1q10 -2 17.5 -10.5t7.5 -18.5v-224l158 158q7 7 18 8t19 -6l106 -106q7 -8 6 -19t-8 -…
13 …-14.5t14.5 -35.5v-350h350q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t-35.5 -14.5h-350v-350q…
15 …-5t-5.5 -13l-364 -364q-6 -6 -11 -18h268q10 0 13 -6t-3 -14l-120 -160q-6 -8 -18 -14t-22 -6h-125v-100…
16 <glyph unicode="&#x2000;" horiz-adv-x="650" />
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/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
[all …]
H A Dsha2-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
32 add t1.4s, v\s0\().4s, \rc\().4s
37 add t0.4s, v\s0\().4s, \rc\().4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
51 * The SHA-256 round constants
81 ld1 { v0.4s- v3.4s}, [x8], #64
82 ld1 { v4.4s- v7.4s}, [x8], #64
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/openbmc/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
39 .size \func, . - \func
43 * This defines the normal kernel pt-regs layout.
45 * regs 9-15 preserved by C code
46 * regs 16-18 saved by PAL-code
47 * regs 29-30 saved and set up by PAL-code
48 * JRP - Save regs 16-18 in a special area of the stack, so that
49 * the palcode-provided values are available to the signal handler.
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
247 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
248 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
316 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
318 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
342 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
343 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
361 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
362 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
366 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
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/openbmc/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
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H A Dhantro_g1_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define G1_REG_CONFIG_DEC_OUTSWAP32_E BIT(19)
56 #define G1_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19)
75 #define G1_REG_DEC_CTRL1_MB_WIDTH_OFF(x) (((x) & 0xf) << 19)
88 #define G1_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 19)
147 #define G1_REG_DEC_CTRL4_TTMBF BIT(19)
179 #define G1_REG_DEC_CTRL5_REF_DIST_FWD(x) (((x) & 0x1f) << 19)
196 #define G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19)
293 #define G1_REG_REF_BUF_CTRL_REFBU_THR(x) (((x) & 0xfff) << 19)
300 #define G1_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 19)
[all …]
H A Dhantro_g1_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
80 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) argument
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) argument
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) argument
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) argument
109 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) argument
116 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) argument
122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) argument
124 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
125 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
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/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
118 #define CCM_CCR_OSCNT(v) ((v) & 0xff) argument
120 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
121 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
122 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) argument
126 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) argument
137 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) argument
138 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) argument
142 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) argument
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/openbmc/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
33 #define SUN6I_CSI_IF_CFG_FIELD_POSITIVE (0 << 19)
34 #define SUN6I_CSI_IF_CFG_FIELD_NEGATIVE (1 << 19)
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20)) argument
[all …]
/openbmc/openbmc/poky/meta/recipes-core/ifupdown/files/
H A Dtweak-ptest-script.patch4 Subject: [PATCH] Tweak tests of ifupdown to make it work with oe-core ptest
7 Upstream-Status: Inappropriate [oe-core specific]
9 Signed-off-by: Kai Kang <kai.kang@windriver.com>
10 ---
11 tests/testbuild-linux | 11 ++++++-----
12 1 file changed, 6 insertions(+), 5 deletions(-)
14 diff --git a/tests/testbuild-linux b/tests/testbuild-linux
16 --- a/tests/testbuild-linux
17 +++ b/tests/testbuild-linux
18 @@ -1,6 +1,7 @@
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_esai.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC
52 /* ESAI Control Register -- REG_ESAI_ECR 0x8 */
53 #define ESAI_ECR_ETI_SHIFT 19
72 /* ESAI Status Register -- REG_ESAI_ESR 0xC */
108 * Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10
109 * Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18
111 #define ESAI_xFCR_TIEN_SHIFT 19
114 #define ESAI_xFCR_REXT_SHIFT 19
119 #define ESAI_xFCR_xWA_MASK (((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT)
[all …]
/openbmc/linux/include/linux/
H A Dinet.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dlnbp21.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * lnbp21.h - driver for lnb supply and control ic lnbp21
21 /* [RW] 0=low voltage (13/14V, vert pol)
22 1=high voltage (18/19V,horiz pol) */
24 /* [RW] increase LNB voltage by 1V:
25 0=13/18V; 1=14/19V */
31 0:Iout=500-650mA Isc=300mA
32 1:Iout=400-550mA Isc=200mA */
34 /* [RW] short-circuit protect:
/openbmc/linux/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/
H A Dsun8i_a83t_mipi_csi2_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2020-2022 Bootlin
33 #define SUN8I_A83T_MIPI_CSI2_INT_STA0_LS_LE_ERR_DT3 BIT(19)
58 #define SUN8I_A83T_MIPI_CSI2_INT_STA1_LS_LE_ERR_DT7 BIT(19)
88 #define SUN8I_A83T_MIPI_CSI2_INT_MSK0_LS_LE_ERR_DT3 BIT(19)
134 #define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v) (((v) << 18) & \ argument
136 #define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v) ((((v) - 1) << 16) & \ argument
138 #define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v) ((((v) - 1) << 4) & \ argument
147 (((ch) - 4) * 8 + 6))
149 (((ch) - 4) * 8))
/openbmc/openbmc/poky/documentation/overview-manual/svg/
H A Dgit-workflow.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
6 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
10 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
17 sodipodi:docname="git-workflow.svg"
18 inkscape:version="1.0.2 (394de47547, 2021-03-26)">
33 <inkscape:path-effect
35 id="path-effect6121"
56 transform="scale(-0.6)"
57 …d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
58 …style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.625;stroke-line…
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/openbmc/linux/sound/soc/qcom/
H A Dlpass-sc7280.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
5 * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
13 #include <dt-bindings/sound/sc7180-lpass.h>
15 #include "lpass-lpaif-reg.h"
113 struct lpass_variant *v = drvdata->variant; in sc7280_lpass_alloc_dma_channel() local
119 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map, in sc7280_lpass_alloc_dma_channel()
120 v->rdma_channels); in sc7280_lpass_alloc_dma_channel()
122 if (chan >= v->rdma_channels) in sc7280_lpass_alloc_dma_channel()
123 return -EBUSY; in sc7280_lpass_alloc_dma_channel()
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-sun6i-r.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * bit 0 bits 1-15^ bits 19-31
9 * +---------+ +---------+ +---------+ +---------+
11 * +---------+ +---------+ +---------+ +---------+
14 * +------V------+ +------------+ | | | +--V------V--+ |
17 * +-------------+ +------------+ | | | +------------+ |
19 * +--V-------V--+ +--V--+ | +--V--+ | +--V--+
22 * +-------------+ | N+d | | | m | | | m+7 |
23 * | | +-----+ | +-----+ | +-----+
25 * +-------V-+ +-V----------+ +---------V--+ +--------V--------+
[all …]
/openbmc/openbmc/poky/documentation/template/
H A Dtemplate.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
9 inkscape:version="1.1 (ce6663b3b7, 2021-05-25)"
11 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
15 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
31 <inkscape:path-effect
33 id="path-effect6121"
55 transform="scale(-0.6)"
56 …d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
57 …style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.625;stroke-line…
69 transform="scale(-0.6)"
[all …]
/openbmc/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
44 #define EMAC_IEVENT_UN BIT(19)
58 #define EMAC_IMASK_UN BIT(19)
102 /* MII-related definitios */
118 #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ argument
120 #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ argument
122 #define EMAC_MII_DATA(v) (v & 0xffff) argument
127 #define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) argument
129 /* Internal PHY Registers - SGMII */
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
60 * 5 b0 b4 b8 bc 190 194 198 19c
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
154 #define SCALER_INT_EN_ILLEGAL_DST_H_POS (1 << 19)
182 #define SCALER_INT_STATUS_ILLEGAL_DST_H_POS (1 << 19)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
225 #define SCALER_YUV444_2P_VU 19
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
[all …]

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