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/openbmc/linux/Documentation/hwmon/
H A Dltc4245.rst10 Addresses scanned: 0x20-0x3f
20 -----------
28 -----------
38 $ echo ltc4245 0x23 > /sys/bus/i2c/devices/i2c-1/new_device
42 -------------
44 The LTC4245 has built-in limits for over and under current warnings. This
48 into the values specified in the sysfs-interface document. The current readings
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
[all …]
H A Dcorsair-psu.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver corsair-psu
37 -----------
41 These power supplies provide access to a micro-controller with 2 attached
43 power usage and 4 sensors for current levels and additional non-sensor information
47 -------------
51 curr2_input Current on the 12v psu rail
52 curr2_crit Current max critical value on the 12v psu rail
53 curr3_input Current on the 5v psu rail
54 curr3_crit Current max critical value on the 5v psu rail
[all …]
H A Dmc13783-adc.rst1 Kernel driver mc13783-adc
10 Datasheet: https://www.nxp.com/docs/en/data-sheet/MC13783.pdf
16 Datasheet: https://www.nxp.com/docs/en/data-sheet/MC13892.pdf
22 - Sascha Hauer <s.hauer@pengutronix.de>
23 - Luotao Fu <l.fu@pengutronix.de>
26 -----------
29 Among other things they contain a 10-bit A/D converter. The converter has 16
30 (MC13783) resp. 12 (MC13892) channels which can be used in different modes. The
42 - MC13783:
47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
[all …]
/openbmc/linux/lib/crypto/
H A Dblake2s-generic.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
/openbmc/linux/crypto/
H A Dblake2b_generic.c1 // SPDX-License-Identifier: (GPL-2.0-only OR Apache-2.0)
11 * - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0
12 * - OpenSSL license : https://www.openssl.org/source/license.html
13 * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0
25 static const u8 blake2b_sigma[12][16] = {
26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 // load the words on-demand.
59 // Execute a quarter-round of BLAKE2s by mixing two columns or two diagonals.
61 // columns/diagonals. s0-s1 are the word offsets to the message words the first
62 // column/diagonal needs, and likewise s2-s3 for the second column/diagonal.
87 // b = ror32(b ^ c, 12);
95 add \a0, \a0, \b0, ror #12
96 add \a1, \a1, \b1, ror #12
109 eor \b0, \c0, \b0, ror#12
110 eor \b1, \c1, \b1, ror#12
[all …]
H A Dblake2b-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 // M_0-M_3 are occasionally used for other purposes too.
50 // rotation amounts with NEON. (On Cortex-A53 it's the same speed as
51 // vshr.u64 + vsli.u64, while on Cortex-A7 it's faster.)
63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack
65 // pointer points to a 32-byte aligned buffer containing a copy of q8 and q9
66 // (M_0-M_3), so that they can be reloaded if they are used as temporary
67 // registers. The macro arguments s0-s15 give the order in which the message
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dsev-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define GHCB_DATA_LOW 12
13 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
15 #define GHCB_DATA(v) \ argument
16 (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
31 #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) argument
32 #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) argument
33 #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) argument
51 /* GHCBData[31:12] */ \
62 #define GHCB_MSR_REG_GPA_REQ_VAL(v) \ argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
69 #define MXC_CCM_CCR_COSC_EN (0x1 << 12)
80 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) argument
92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) argument
96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) argument
100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) argument
109 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) argument
116 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) argument
122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) argument
126 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) argument
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
118 #define CCM_CCR_OSCNT(v) ((v) & 0xff) argument
122 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) argument
126 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) argument
131 #define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
137 #define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) argument
138 #define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) argument
142 #define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) argument
146 #define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) argument
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
85 ld1 {v\rc1\().2d}, [x4], #16
87 add v5.2d, v\rc0\().2d, v\in0\().2d
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
90 ext v7.16b, v\i1\().16b, v\i2\().16b, #8
91 add v\i3\().2d, v\i3\().2d, v5.2d
93 ext v5.16b, v\in3\().16b, v\in4\().16b, #8
[all …]
/openbmc/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
57 /* Only since sun9i-a80-isp. */
89 #define SUN6I_ISP_MODULE_EN_RGB2RGB BIT(12)
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
[all …]
/openbmc/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20)) argument
72 #define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16)) argument
74 #define SUN6I_CSI_CH_CFG_HFLIP_EN BIT(12)
[all …]
/openbmc/linux/arch/microblaze/lib/
H A Dfastcopy.S2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2008-2009 PetaLogix
4 * Copyright (C) 2008 Jim Law - Iris LP All rights reserved.
21 * Input : Operand1 in Reg r5 - destination address
22 * Operand2 in Reg r6 - source address
23 * Operand3 in Reg r7 - number of bytes to transfer
24 * Output: Result in Reg r3 - starting destinaition address
44 cmpu r4, r4, r7 /* n = c - n (unsigned) */
51 /* n = 4 - n (yields 3, 2, 1 transfers for 1, 2, 3 addr offset) */
53 rsub r7, r4, r7 /* c = c - n adjust c */
[all …]
/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
49 #define ALTERA_TSE_TX_IPG_LENGTH 12
53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
69 #define MAC_CMDCFG_LATE_COL BIT(12)
73 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
85 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
87 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) argument
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
45 * the palcode-provided values are available to the signal handler.
[all …]
/openbmc/linux/drivers/hwmon/
H A Dabituguru3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2008 Hans de Goede <hdegoede@redhat.com>
25 #include <linux/hwmon-sysfs.h>
55 * cpu-speed independent, since the ISA-bus and not the CPU should be the
85 #define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13)
90 #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
96 (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
104 /* Two i/o-ports are used by uGuru */
111 * of the DATA register (0-255) on failure.
113 #define ABIT_UGURU3_SUCCESS -1
[all …]
H A Dintel-m10-bmc-hwmon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
10 #include <linux/mfd/intel-m10-bmc.h>
53 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Voltage" },
54 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1, "1.2V Voltage" },
55 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Voltage" },
56 { 0x158, 0x0, 0x0, 0x0, 0x0, 1, "1.8V Voltage" },
57 { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "3.3V Voltage" },
62 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Current" },
63 { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Current" },
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dcrm_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
206 #define MXC_CCM_CCR_COSC_EN (1 << 12)
228 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
283 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
284 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
324 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
325 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) argument
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) argument
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) argument
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/fonts/
H A Dglyphicons-halflings-regular.svg2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd" >
6 <font id="glyphicons_halflingsregular" horiz-adv-x="1200" >
7 <font-face units-per-em="1200" ascent="960" descent="-240" />
8 <missing-glyph horiz-adv-x="500" />
9 <glyph horiz-adv-x="0" />
10 <glyph horiz-adv-x="400" />
12 …-1.5t30 -3.5l11 -1q10 -2 17.5 -10.5t7.5 -18.5v-224l158 158q7 7 18 8t19 -6l106 -106q7 -8 6 -19t-8 -…
13 …-14.5t14.5 -35.5v-350h350q21 0 35.5 -14.5t14.5 -35.5v-200q0 -21 -14.5 -35.5t-35.5 -14.5h-350v-350q…
15 …-5t-5.5 -13l-364 -364q-6 -6 -11 -18h268q10 0 13 -6t-3 -14l-120 -160q-6 -8 -18 -14t-22 -6h-125v-100…
16 <glyph unicode="&#x2000;" horiz-adv-x="650" />
[all …]
H A Dfontawesome-webfont.svg2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd" >
6 <font id="fontawesomeregular" horiz-adv-x="1536" >
7 <font-face units-per-em="1792" ascent="1536" descent="-256" />
8 <missing-glyph horiz-adv-x="448" />
9 <glyph unicode=" " horiz-adv-x="448" />
10 <glyph unicode="&#x09;" horiz-adv-x="448" />
11 <glyph unicode="&#xa0;" horiz-adv-x="448" />
12 <glyph unicode="&#xa8;" horiz-adv-x="1792" />
13 <glyph unicode="&#xa9;" horiz-adv-x="1792" />
14 <glyph unicode="&#xae;" horiz-adv-x="1792" />
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Dmodule.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 * The auipc+jalr instruction pair can reach any PC-relative offset
19 * in the range [-2^31 - 2^11, 2^31 - 2^11)
26 return (-(1L << 31) - (1L << 11)) <= val && val < ((1L << 31) - (1L << 11)); in riscv_insn_valid_32bit_offset()
30 static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v) in apply_r_riscv_32_rela() argument
32 if (v != (u32)v) { in apply_r_riscv_32_rela()
33 pr_err("%s: value %016llx out of range for 32-bit field\n", in apply_r_riscv_32_rela()
34 me->name, (long long)v); in apply_r_riscv_32_rela()
35 return -EINVAL; in apply_r_riscv_32_rela()
37 *location = v; in apply_r_riscv_32_rela()
[all …]
/openbmc/linux/include/linux/
H A Dinet.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * $Id: Space.c,v 0.8.4.5 1992/12/12 19:25:04 bir7 Exp $
13 * $Id: arp.c,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
14 * $Id: arp.h,v 0.8.4.6 1993/01/28 22:30:00 bir7 Exp $
15 * $Id: dev.c,v 0.8.4.13 1993/01/23 18:00:11 bir7 Exp $
16 * $Id: dev.h,v 0.8.4.7 1993/01/23 18:00:11 bir7 Exp $
17 * $Id: eth.c,v 0.8.4.4 1993/01/22 23:21:38 bir7 Exp $
18 * $Id: eth.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $
19 * $Id: icmp.c,v 0.8.4.9 1993/01/23 18:00:11 bir7 Exp $
20 * $Id: icmp.h,v 0.8.4.2 1992/11/15 14:55:30 bir7 Exp $
[all …]
/openbmc/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
[all …]
/openbmc/linux/include/video/
H A Dgbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/video/gbe.h -- SGI GBE (Graphics Back End)
20 uint32_t _pad0[0x010000/4 - 8];
82 ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
83 #define GET(v, msb, lsb) \ argument
84 ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
85 #define SET(v, f, msb, lsb) \ argument
86 ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
88 #define GET_GBE_FIELD(reg, field, v) \ argument
89 GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
[all …]

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