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/openbmc/u-boot/arch/arm/lib/
H A Dpsci-dt.c1 // SPDX-License-Identifier: GPL-2.0+
16 int fdt_psci(void *fdt) in fdt_psci() argument
24 nodeoff = fdt_path_offset(fdt, "/cpus"); in fdt_psci()
30 /* add 'enable-method = "psci"' to each cpu node */ in fdt_psci()
31 for (tmp = fdt_first_subnode(fdt, nodeoff); in fdt_psci()
33 tmp = fdt_next_subnode(fdt, tmp)) { in fdt_psci()
37 prop = fdt_get_property(fdt, tmp, "device_type", &len); in fdt_psci()
42 if (strcmp(prop->data, "cpu")) in fdt_psci()
50 fdt_setprop_string(fdt, tmp, "enable-method", "psci"); in fdt_psci()
53 nodeoff = fdt_path_offset(fdt, "/psci"); in fdt_psci()
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/openbmc/u-boot/lib/
H A DKconfig4 bool "Enable Software based BCH ECC"
7 This is used by SoC platforms which do not have built-in ELM
13 Enabling this option will pass "-O2" to gcc when compiling
19 bool "Enable Dynamic tables for CRC"
21 Enable this option to calculate entries for CRC tables at runtime.
27 Enable this option if architecture provides io{read,write}{8,16,32}
86 This option allows you to use the built-in libgcc implementation
87 of U-Boot instead of the one provided by the compiler.
99 bool "Enable tiny printf() version"
119 bool "Enable regular expression support"
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/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream()
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
54 dev_err(clk->dev, "Invalid control register\n"); in socfpga_a10_clk_get_upstream()
55 return -EINVAL; in socfpga_a10_clk_get_upstream()
58 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_upstream()
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/openbmc/u-boot/include/configs/
H A Dib62x0.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011-2012
28 * mv-common.h should be defined after CMD configs since it used them
29 * to enable certain macros
31 #include "mv-common.h"
50 "ubifsload 0x700000 ${fdt}; " \
52 "fdt addr 0x700000; fdt resize; fdt chosen; " \
53 "bootz 0x800000 - 0x700000"
60 "fdt=/boot/ib62x0.dtb\0" \
67 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
H A Dnsa310s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * mv-common.h should be defined after CMD configs since it used them
25 * to enable certain macros
27 #include "mv-common.h"
42 "ubifsload 0x700000 ${fdt}; " \
44 "fdt addr 0x700000; fdt resize; fdt chosen; " \
45 "bootz 0x800000 - 0x700000"
52 "fdt=/boot/nsa310s.dtb\0" \
58 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
H A Dguruplug.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2009-2014
6 * Written-by: Siddarth Gore <gores@marvell.com>
23 * mv-plug-common.h should be defined after CMD configs since it used them
24 * to enable certain macros
26 #include "mv-plug-common.h"
41 * Environment is right behind U-Boot in flash. Make sure U-Boot
54 "ubifsload 0x700000 ${fdt}; " \
56 "fdt addr 0x700000; fdt resize; fdt chosen; " \
57 "bootz 0x800000 - 0x700000"
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H A Dxpedite550x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
85 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
88 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
91 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
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H A Dxpedite537x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
81 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
82 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
83 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
84 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
85 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
86 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
87 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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H A Dxpedite520x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2004-2008 Freescale Semiconductor, Inc.
23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
69 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
70 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
71 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
72 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
73 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
74 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
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H A Dxpedite517x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 * Base addresses -- Note these are effective addresses where the
90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
95 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dspin_table.c1 // SPDX-License-Identifier: GPL-2.0+
11 int spin_table_update_dt(void *fdt) in spin_table_update_dt() argument
17 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt()
20 cpus_offset = fdt_path_offset(fdt, "/cpus"); in spin_table_update_dt()
22 return -ENODEV; in spin_table_update_dt()
24 for (offset = fdt_first_subnode(fdt, cpus_offset); in spin_table_update_dt()
26 offset = fdt_next_subnode(fdt, offset)) { in spin_table_update_dt()
27 prop = fdt_getprop(fdt, offset, "device_type", NULL); in spin_table_update_dt()
33 * spin-table. Otherwise, just return successfully to not in spin_table_update_dt()
36 prop = fdt_getprop(fdt, offset, "enable-method", NULL); in spin_table_update_dt()
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/openbmc/u-boot/arch/nios2/lib/
H A Dbootm.c1 // SPDX-License-Identifier: GPL-2.0+
9 #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
13 void (*kernel)(int, int, int, char *) = (void *)images->ep; in do_bootm_linux()
15 ulong initrd_start = images->rd_start; in do_bootm_linux()
16 ulong initrd_end = images->rd_end; in do_bootm_linux()
20 if (images->ft_len) in do_bootm_linux()
21 of_flat_tree = images->ft_addr; in do_bootm_linux()
42 debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end); in do_bootm_linux()
46 * r6 : initrd end or fdt in do_bootm_linux()
48 * fdt is passed to kernel via r6, the same as initrd_end. fdt will be in do_bootm_linux()
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/openbmc/u-boot/doc/
H A DREADME.falcon1 U-Boot Falcon Mode
5 ------------
11 to boot a Linux kernel (or whatever image) without a full blown U-Boot.
14 U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
15 image. In most implementations, SPL is used to start U-Boot when booting from
16 a mass storage, such as NAND or SD-Card. SPL has now support for other media,
19 copies U-Boot image into the memory.
22 from SPL. A new command is added to U-Boot to prepare the parameters that SPL
31 To boot the kernel, these steps under a Falcon-aware U-Boot are required:
33 1. Boot the board into U-Boot.
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H A DREADME.fdt-control1 # SPDX-License-Identifier: GPL-2.0+
5 Device Tree Control in U-Boot
8 This feature provides for run-time configuration of U-Boot via a flat
9 device tree (fdt). U-Boot configuration has traditionally been done
11 make it possible for a single U-Boot binary to support multiple boards,
13 tree (fdt). This is the approach recently taken by the ARM Linux kernel
16 The fdt is a convenient vehicle for implementing run-time configuration
21 Finally, there is already excellent infrastructure for the fdt: a
23 format, and a library is already available in U-Boot (libfdt) for
27 and embedding it in your U-Boot image. This is useful since it allows
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dmisc_s10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
37 -1,
57 return -EINVAL; in socfpga_phymode_setup()
67 return -EINVAL; in socfpga_phymode_setup()
69 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, in socfpga_phymode_setup()
78 const void *fdt = gd->fdt_blob; in socfpga_set_phymode() local
86 count = fdtdec_find_aliases_for_id(fdt, "ethernet", in socfpga_set_phymode()
94 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", in socfpga_set_phymode()
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/openbmc/u-boot/drivers/usb/musb-new/
H A Domap2430.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2005-2007 by Texas Instruments
13 #include <dm/device-internal.h>
20 #include "linux-compat.h"
30 l = musb_readl(musb->mregs, OTG_FORCESTDBY); in omap2430_low_level_exit()
31 l |= ENABLEFORCE; /* enable MSTANDBY */ in omap2430_low_level_exit()
32 musb_writel(musb->mregs, OTG_FORCESTDBY, l); in omap2430_low_level_exit()
39 l = musb_readl(musb->mregs, OTG_FORCESTDBY); in omap2430_low_level_init()
41 musb_writel(musb->mregs, OTG_FORCESTDBY, l); in omap2430_low_level_init()
52 (struct omap_musb_board_data *)musb->controller; in omap2430_musb_init()
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/openbmc/u-boot/
H A DKconfig3 # see the file Documentation/kbuild/kconfig-language.txt in the
6 mainmenu "U-Boot $UBOOTVERSION Configuration"
12 # Allow defaults in arch-specific code to override any given here
24 string "Local version - append to U-Boot release"
26 Append an extra string to the end of your U-Boot version.
41 A string of the format -gxxxxxxxx will be added to the localversion
42 if a Git-based tree is found. The string generated by this will be
49 $ git rev-parse --verify HEAD
57 Enabling this option will pass "-Os" instead of "-O2" to gcc
58 resulting in a smaller U-Boot image.
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/openbmc/u-boot/drivers/spi/
H A Dspi-sunxi.c10 * linux/drivers/spi/spi-sun4i.c
12 * Copyright (C) 2012 - 2014 Allwinner Tech
16 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 * SPDX-License-Identifier: GPL-2.0+
77 #define SPI_REG(priv, reg) ((priv)->base + \
78 (priv)->variant->regs[reg])
79 #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
144 while (len--) { in sun4i_spi_drain_fifo()
146 if (priv->rx_buf) in sun4i_spi_drain_fifo()
147 *priv->rx_buf++ = byte; in sun4i_spi_drain_fifo()
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/openbmc/u-boot/doc/uImage.FIT/
H A Dsignature.txt1 U-Boot FIT Signature Verification
5 ------------
12 key is kept secret and the public key is stored in a non-volatile place,
15 See verified-boot.txt for more general information on verified boot.
19 --------
24 - hash an image in the FIT
25 - sign the hash with a private key to produce a signature
26 - store the resulting signature in the FIT
30 - read the FIT
31 - obtain the public key
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/openbmc/u-boot/drivers/net/ti/
H A Dkeystone_net.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
32 #define emac_gigabit_enable(x) /* no gigabit to enable */
108 * Check if link detected is giga-bit in keystone2_eth_gigabit_enable()
109 * If Gigabit mode detected, enable gigbit in MAC in keystone2_eth_gigabit_enable()
111 if (priv->has_mdio) { in keystone2_eth_gigabit_enable()
112 if (priv->phydev->speed != 1000) in keystone2_eth_gigabit_enable()
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/openbmc/qemu/hw/arm/
H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
57 #include "qemu/error-report.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/pci-bridge/pci_expander_bridge.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/core/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
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/openbmc/u-boot/test/
H A Drun3 # Script to run all U-Boot tests that use sandbox.
10 echo -n "$1: "
13 [ $? -ne 0 ] && failures=$((failures+1))
22 run_test "sandbox" ./test/py/test.py --bd sandbox --build -m "${mark_expr}"
25 run_test "sandbox_spl" ./test/py/test.py --bd sandbox_spl --build \
26 -k 'test_ofplatdata or test_handoff'
28 # Run tests for the flat-device-tree version of sandbox. This is a special
29 # build which does not enable CONFIG_OF_LIVE for the live device tree, so we can
32 run_test "sandbox_flattree" ./test/py/test.py --bd sandbox_flattree --build \
33 -k test_ut
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/openbmc/u-boot/arch/arm/mach-meson/
H A Dboard-gx.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/meson-vpu.h>
28 void meson_init_reserved_memory(void *fdt) in meson_init_reserved_memory() argument
36 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 in meson_init_reserved_memory()
37 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL in meson_init_reserved_memory()
38 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL in meson_init_reserved_memory()
60 meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE); in meson_init_reserved_memory()
64 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); in meson_init_reserved_memory()
68 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); in meson_init_reserved_memory()
71 meson_vpu_rsv_fb(fdt); in meson_init_reserved_memory()
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/openbmc/u-boot/drivers/power/
H A Dexynos-tmu.c6 * EXYNOS - Thermal Management Unit
17 * MA 02111-1307 USA
64 /* Pre-defined values and thresholds for calibration of current temperature */
66 /* pre-defined temperature thresholds */
68 /* pre-defined efuse range minimum value */
70 /* pre-defined efuse value for temperature calibration */
72 /* pre-defined efuse range maximum value */
84 /* pre-defined values for calibration and thresholds */
108 struct exynos5_tmu_reg *reg = info->tmu_base; in get_cur_temp()
117 if (info->tmu_state == TMU_STATUS_NORMAL) { in get_cur_temp()
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/openbmc/qemu/hw/mips/
H A Dboston.c25 #include "hw/char/serial-mm.h"
27 #include "hw/ide/ahci-pci.h"
29 #include "hw/loader-fit.h"
32 #include "hw/pci-host/xilinx-pcie.h"
33 #include "hw/qdev-clock.h"
34 #include "hw/qdev-properties.h"
36 #include "qemu/error-report.h"
37 #include "qemu/guest-random.h"
49 #define TYPE_BOSTON "mips-boston"
158 if (event == CHR_EVENT_OPENED && !s->lcd_inited) { in boston_lcd_event()
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