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/openbmc/u-boot/arch/arm/mach-snapdragon/
H A Dclock-snapdragon.c1 // SPDX-License-Identifier: BSD-3-Clause
11 #include <clk-uclass.h>
16 #include "clock-snapdragon.h"
35 if (readl(base + gpll0->status) & gpll0->status_bit) in clk_enable_gpll0()
38 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); in clk_enable_gpll0()
40 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) in clk_enable_gpll0()
48 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) in clk_enable_vote_clk() argument
52 setbits_le32(base + vclk->ena_vote, vclk->vote_bit); in clk_enable_vote_clk()
54 val = readl(base + vclk->cbcr_reg); in clk_enable_vote_clk()
84 /* NOT(N-M) value for MND divider. */ in clk_rcg_set_rate_mnd()
[all …]
H A Dclock-snapdragon.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
41 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c37 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
44 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
52 struct radeon_mode_info *minfo = &rdev->mode_info; in rs780_get_pm_mode_parameters()
58 pi->crtc_id = 0; in rs780_get_pm_mode_parameters()
59 pi->refresh_rate = 60; in rs780_get_pm_mode_parameters()
61 for (i = 0; i < rdev->num_crtc; i++) { in rs780_get_pm_mode_parameters()
62 crtc = (struct drm_crtc *)minfo->crtcs[i]; in rs780_get_pm_mode_parameters()
63 if (crtc && crtc->enabled) { in rs780_get_pm_mode_parameters()
65 pi->crtc_id = radeon_crtc->crtc_id; in rs780_get_pm_mode_parameters()
66 if (crtc->mode.htotal && crtc->mode.vtotal) in rs780_get_pm_mode_parameters()
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H A Dradeon_uvd.c15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
74 switch (rdev->family) { in radeon_uvd_init()
134 return -EINVAL; in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init()
143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init()
149 r = radeon_ucode_validate(rdev->uvd_fw); in radeon_uvd_init()
[all …]
H A Dsumo_dpm.c76 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps()
83 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
156 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
184 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
196 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
217 if (rdev->family == CHIP_PALM) in sumo_gfx_powergating_initialize()
226 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
232 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
251 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
259 if (rdev->family == CHIP_PALM) { in sumo_gfx_powergating_initialize()
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H A Dtrinity_dpm.c306 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
313 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
348 if (pi->override_dynamic_mgpg && (hw_rev == 0)) in trinity_gfx_powergating_initialize()
505 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
507 if (pi->enable_mg_clock_gating) in trinity_enable_clock_power_gating()
509 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
511 if (pi->enable_mg_clock_gating) { in trinity_enable_clock_power_gating()
515 if (pi->enable_gfx_clock_gating) in trinity_enable_clock_power_gating()
517 if (pi->enable_gfx_dynamic_mgpg) in trinity_enable_clock_power_gating()
519 if (pi->enable_gfx_power_gating) in trinity_enable_clock_power_gating()
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H A Drv6xx_dpm.c38 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
63 for (i = 0; i < rdev->usec_timeout; i++) { in rv6xx_force_pcie_gen1()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
167 pi->spll_ref_div, in rv6xx_output_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Daspeed-video.txt7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine" or
9 "aspeed,ast2600-video-engine"
10 - reg: contains the offset and length of the VE memory region
11 - clocks: clock specifiers for the syscon clocks associated with
12 the VE (ordering must match the clock-names property)
13 - clock-names: "vclk" and "eclk"
14 - resets: reset specifier for the syscon reset associated with
16 - interrupts: the interrupt associated with the VE on this platform
19 - memory-region:
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/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drzg2l_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0
41 struct clk *vclk; member
165 iowrite32(data, dsi->mmio + reg); in rzg2l_mipi_dsi_phy_write()
170 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_write()
175 return ioread32(dsi->mmio + reg); in rzg2l_mipi_dsi_phy_read()
180 return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_read()
183 /* -----------------------------------------------------------------------------
202 if (hsfreq <= dphy_timings->hsfreq_max) in rzg2l_mipi_dsi_dphy_init()
218 DSIDPHYTIM0_T_INIT(dphy_timings->t_init); in rzg2l_mipi_dsi_dphy_init()
219 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) | in rzg2l_mipi_dsi_dphy_init()
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/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,fimd.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,s3c2443-fimd
19 - samsung,s3c6400-fimd
20 - samsung,s5pv210-fimd
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
50 struct clk *vclk; member
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank()
88 if (ctx->suspended) in decon_wait_for_vblank()
91 atomic_set(&ctx->wait_vsync_event, 1); in decon_wait_for_vblank()
97 if (!wait_event_timeout(ctx->wait_vsync_queue, in decon_wait_for_vblank()
98 !atomic_read(&ctx->wait_vsync_event), in decon_wait_for_vblank()
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in decon_wait_for_vblank()
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/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
63 pclk_freq = arb->pclk_khz; in nv04_calc_arb()
64 mclk_freq = arb->mclk_khz; in nv04_calc_arb()
65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb()
66 pagemiss = arb->mem_page_miss; in nv04_calc_arb()
67 cas = arb->mem_latency; in nv04_calc_arb()
68 bpp = arb->bpp; in nv04_calc_arb()
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
97 mclk_extra--; in nv04_calc_arb()
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Dvt1636.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
16 /* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
18 /* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
20 /* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
22 /* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
24 /* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
46 viafb_i2c_readbyte(plvds_chip_info->i2c_port, in viafb_gpio_i2c_read_lvds()
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/openbmc/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-cru.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 #include <media/v4l2-async.h>
14 #include <media/v4l2-dev.h>
15 #include <media/v4l2-device.h>
16 #include <media/videobuf2-v4l2.h>
34 * enum rzg2l_cru_dma_state - DMA states
61 * struct rzg2l_cru_dev - Renesas CRU device structure
69 * @vclk: CRU Main clock
106 struct clk *vclk; member
H A Drzg2l-csi2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mc.h>
25 #include <media/v4l2-subdev.h>
60 /* D-PHY Control Register 0 */
65 /* D-PHY Timing Register 0 */
70 /* D-PHY Timing Register 1 */
[all …]
H A Drzg2l-core.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Based on Renesas R-Car VIN
8 * Copyright (C) 2011-2013 Renesas Solutions Corp.
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-mc.h>
24 #include "rzg2l-cru.h"
35 /* -----------------------------------------------------------------------------
49 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete()
51 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete()
63 * Create media device link between CSI-2 <-> CRU IP in rzg2l_cru_group_notify_complete()
[all …]
/openbmc/linux/drivers/video/fbdev/riva/
H A Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
[all …]
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
24 - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
25 - renesas,r9a07g054-mipi-dsi # RZ/V2L
26 - const: renesas,rzg2l-mipi-dsi
33 - description: Sequence operation channel 0 interrupt
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/openbmc/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
73 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
79 * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
82 * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
84 * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
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/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c27 #include "atom-types.h"
53 if (smu8_magic != hw_ps->magic) in cast_smu8_power_state()
62 if (smu8_magic != hw_ps->magic) in cast_const_smu8_power_state()
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
78 for (i = 0; i < (int)ptable->count; i++) { in smu8_get_eclk_level()
79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
86 for (i = ptable->count - 1; i >= 0; i--) { in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
109 for (i = 0; i < (int)table->count; i++) { in smu8_get_sclk_level()
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/openbmc/linux/drivers/video/fbdev/sis/
H A Dinit.c10 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
27 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
55 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
81 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable; in InitCommonPointer()
82 SiS_Pr->SiS_StResInfo = SiS_StResInfo; in InitCommonPointer()
83 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo; in InitCommonPointer()
84 SiS_Pr->SiS_StandTable = SiS_StandTable; in InitCommonPointer()
86 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming; in InitCommonPointer()
87 SiS_Pr->SiS_PALTiming = SiS_PALTiming; in InitCommonPointer()
88 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing; in InitCommonPointer()
[all …]
/openbmc/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_drm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
41 args->pitch = logicvc->config.row_stride * DIV_ROUND_UP(args->bpp, 8); in logicvc_drm_gem_dma_dumb_create()
51 .name = "logicvc-drm",
64 .name = "logicvc-drm",
74 regmap_read(logicvc->regmap, LOGICVC_INT_STAT_REG, &stat); in logicvc_drm_irq_handler()
77 regmap_write(logicvc->regmap, LOGICVC_INT_STAT_REG, stat); in logicvc_drm_irq_handler()
89 struct drm_device *drm_dev = &logicvc->drm_dev; in logicvc_drm_config_parse()
90 struct device *dev = drm_dev->dev; in logicvc_drm_config_parse()
91 struct device_node *of_node = dev->of_node; in logicvc_drm_config_parse()
[all …]

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