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Searched defs:regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7159 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h77 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h64 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h81 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12412 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h12277 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11525 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13008 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX … macro