Home
last modified time | relevance | path

Searched defs:pll_div (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h60 struct pll_div { struct
61 u32 refdiv;
62 u32 fbdiv;
63 u32 postdiv1;
64 u32 postdiv2;
65 u32 frac;
H A Dcru_rk322x.h61 struct pll_div { struct
62 u32 refdiv;
63 u32 fbdiv;
64 u32 postdiv1;
65 u32 postdiv2;
66 u32 frac;
H A Dcru_rk3128.h63 struct pll_div { struct
64 u32 refdiv;
65 u32 fbdiv;
66 u32 postdiv1;
67 u32 postdiv2;
68 u32 frac;
H A Dcru_rv1108.h53 struct pll_div { struct
54 u32 refdiv;
55 u32 fbdiv;
56 u32 postdiv1;
57 u32 postdiv2;
58 u32 frac;
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c36 struct pll_div { struct
37 u32 nr;
38 u32 nf;
39 u32 no;
H A Dclk_rk3328.c20 struct pll_div { struct
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); argument
H A Dclk_rk3368.c29 struct pll_div { struct
50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); argument
H A Dclk_rk3288.c34 struct pll_div { struct
35 u32 nr;
36 u32 nf;
37 u32 no;
H A Dclk_rk3399.c32 struct pll_div { struct
50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); argument
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dcpu.c115 static unsigned pll_div(volatile void *pllbase, unsigned offset) in pll_div() function
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c775 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video()
898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c551 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video()
626 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local