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Searched defs:pll (Results 1 – 25 of 72) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c26 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) in imx_decode_pll()
46 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m() local
58 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk() local
72 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk() local
87 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk() local
99 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk() local
118 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1() local
125 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2() local
132 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3() local
139 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4() local
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dspeed.c21 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
57 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c59 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
73 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5441x_clocks() local
132 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5445x_clocks() local
/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c57 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
74 pll_t *pll = (pll_t *)MMAP_PLL; in get_clocks() local
H A Dcpu_init.c33 pll_t *pll = (pll_t *)MMAP_PLL; in cpu_init_f() local
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c82 static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, in __mtk_pll_recalc_rate()
115 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_pll_set_rate_regs() local
152 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_pll_calc_values() local
187 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_apmixedsys_get_rate() local
205 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_apmixedsys_enable() local
234 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; in mtk_apmixedsys_disable() local
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h70 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) argument
94 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) argument
100 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) argument
110 #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) argument
137 #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) argument
142 #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) argument
144 #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) argument
151 #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) argument
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h53 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) argument
54 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) argument
55 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) argument
57 #define pllctl_reg_rmw(pll, reg, mask, val) \ argument
61 #define pllctl_reg_setbits(pll, reg, mask) \ argument
64 #define pllctl_reg_clrbits(pll, reg, mask) \ argument
/openbmc/u-boot/arch/m68k/cpu/mcf523x/
H A Dspeed.c23 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
/openbmc/u-boot/board/freescale/s32v234evb/
H A Dclock.c17 static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) in select_pll_source_clk()
81 static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, in program_pll()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c92 struct clk_pll *pll = get_pll(clkid); in clock_ll_read_pll() local
116 struct clk_pll *pll = NULL; in clock_start_pll() local
265 struct clk_pll *pll = get_pll(clkid); in clock_set_pllout() local
534 struct clk_pll *pll; in clock_get_rate() local
591 struct clk_pll *pll; in clock_set_rate() local
674 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); in clock_verify() local
H A Dcpu.c170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate()
231 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; in init_pllx() local
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c53 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
144 pll_t *pll = (pll_t *)(MMAP_PLL); in clock_pll() local
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c203 static void pll_update(RccPllState *pll, bool bypass_source) in pll_update()
311 static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier) in pll_set_vco_multiplier()
331 static void pll_set_enable(RccPllState *pll, bool enabled) in pll_set_enable()
341 static void pll_set_channel_enable(RccPllState *pll, in pll_set_channel_enable()
359 static void pll_set_channel_divider(RccPllState *pll, in pll_set_channel_divider()
1404 RccPllState *pll = &s->plls[i]; in stm32l4x5_rcc_realize() local
H A Dbcm2835_cprman.c67 static bool pll_is_locked(const CprmanPllState *pll) in pll_is_locked()
73 static void pll_update(CprmanPllState *pll) in pll_update()
201 CprmanPllState *pll) in pll_update_all_channels()
738 CprmanPllState *pll = &s->plls[i]; in cprman_realize() local
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c221 int pll; in init_plls() local
279 static unsigned long pll_freq_get(int pll) in pll_freq_get()
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dclk.c34 u32 val, xtal, pll, div; in get_clocks() local
/openbmc/u-boot/board/ti/ks2_evm/
H A Dboard_k2l.c63 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
H A Dboard_k2e.c72 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
H A Dboard_k2hk.c75 struct pll_init_data *get_pll_init_data(int pll) in get_pll_init_data()
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dclk.c34 u32 val, ctrl, xtal, pll, div; in get_clocks() local
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Demif4.c70 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, in config_ddr()
/openbmc/u-boot/arch/arm/cpu/armv7/iproc-common/
H A Darmpll.c41 uint32_t pll; in armpll_config() local
/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c27 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, in get_pllfreq()
82 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, in decode_pll()
/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.c172 enum zynq_clk pll; in zynq_clk_get_cpu_rate() local
242 enum zynq_clk pll; in zynq_clk_get_peripheral_rate() local
317 enum zynq_clk pll; in zynq_clk_set_peripheral_rate() local

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