1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4 //
5 // Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
7 //
8 // Based on:
9 //
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
11 //
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
13 //
14
15 #include <asm/unaligned.h>
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23
24 #include "mcp251xfd.h"
25
26 #define DEVICE_NAME "mcp251xfd"
27
28 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
29 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
30 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
31 MCP251XFD_QUIRK_ECC,
32 .model = MCP251XFD_MODEL_MCP2517FD,
33 };
34
35 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
36 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
37 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
38 .model = MCP251XFD_MODEL_MCP2518FD,
39 };
40
41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
44 .model = MCP251XFD_MODEL_MCP251863,
45 };
46
47 /* Autodetect model, start with CRC enabled. */
48 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
49 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
50 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
51 .model = MCP251XFD_MODEL_MCP251XFD,
52 };
53
54 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
55 .name = DEVICE_NAME,
56 .tseg1_min = 2,
57 .tseg1_max = 256,
58 .tseg2_min = 1,
59 .tseg2_max = 128,
60 .sjw_max = 128,
61 .brp_min = 1,
62 .brp_max = 256,
63 .brp_inc = 1,
64 };
65
66 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
67 .name = DEVICE_NAME,
68 .tseg1_min = 1,
69 .tseg1_max = 32,
70 .tseg2_min = 1,
71 .tseg2_max = 16,
72 .sjw_max = 16,
73 .brp_min = 1,
74 .brp_max = 256,
75 .brp_inc = 1,
76 };
77
__mcp251xfd_get_model_str(enum mcp251xfd_model model)78 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
79 {
80 switch (model) {
81 case MCP251XFD_MODEL_MCP2517FD:
82 return "MCP2517FD";
83 case MCP251XFD_MODEL_MCP2518FD:
84 return "MCP2518FD";
85 case MCP251XFD_MODEL_MCP251863:
86 return "MCP251863";
87 case MCP251XFD_MODEL_MCP251XFD:
88 return "MCP251xFD";
89 }
90
91 return "<unknown>";
92 }
93
94 static inline const char *
mcp251xfd_get_model_str(const struct mcp251xfd_priv * priv)95 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
96 {
97 return __mcp251xfd_get_model_str(priv->devtype_data.model);
98 }
99
mcp251xfd_get_mode_str(const u8 mode)100 static const char *mcp251xfd_get_mode_str(const u8 mode)
101 {
102 switch (mode) {
103 case MCP251XFD_REG_CON_MODE_MIXED:
104 return "Mixed (CAN FD/CAN 2.0)";
105 case MCP251XFD_REG_CON_MODE_SLEEP:
106 return "Sleep";
107 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
108 return "Internal Loopback";
109 case MCP251XFD_REG_CON_MODE_LISTENONLY:
110 return "Listen Only";
111 case MCP251XFD_REG_CON_MODE_CONFIG:
112 return "Configuration";
113 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
114 return "External Loopback";
115 case MCP251XFD_REG_CON_MODE_CAN2_0:
116 return "CAN 2.0";
117 case MCP251XFD_REG_CON_MODE_RESTRICTED:
118 return "Restricted Operation";
119 }
120
121 return "<unknown>";
122 }
123
124 static const char *
mcp251xfd_get_osc_str(const u32 osc,const u32 osc_reference)125 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
126 {
127 switch (~osc & osc_reference &
128 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
129 case MCP251XFD_REG_OSC_PLLRDY:
130 return "PLL";
131 case MCP251XFD_REG_OSC_OSCRDY:
132 return "Oscillator";
133 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
134 return "Oscillator/PLL";
135 }
136
137 return "<unknown>";
138 }
139
mcp251xfd_vdd_enable(const struct mcp251xfd_priv * priv)140 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
141 {
142 if (!priv->reg_vdd)
143 return 0;
144
145 return regulator_enable(priv->reg_vdd);
146 }
147
mcp251xfd_vdd_disable(const struct mcp251xfd_priv * priv)148 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
149 {
150 if (!priv->reg_vdd)
151 return 0;
152
153 return regulator_disable(priv->reg_vdd);
154 }
155
156 static inline int
mcp251xfd_transceiver_enable(const struct mcp251xfd_priv * priv)157 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
158 {
159 if (!priv->reg_xceiver)
160 return 0;
161
162 return regulator_enable(priv->reg_xceiver);
163 }
164
165 static inline int
mcp251xfd_transceiver_disable(const struct mcp251xfd_priv * priv)166 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
167 {
168 if (!priv->reg_xceiver)
169 return 0;
170
171 return regulator_disable(priv->reg_xceiver);
172 }
173
mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv * priv)174 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
175 {
176 int err;
177
178 err = clk_prepare_enable(priv->clk);
179 if (err)
180 return err;
181
182 err = mcp251xfd_vdd_enable(priv);
183 if (err)
184 clk_disable_unprepare(priv->clk);
185
186 /* Wait for oscillator stabilisation time after power up */
187 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
188 2 * MCP251XFD_OSC_STAB_SLEEP_US);
189
190 return err;
191 }
192
mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv * priv)193 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
194 {
195 int err;
196
197 err = mcp251xfd_vdd_disable(priv);
198 if (err)
199 return err;
200
201 clk_disable_unprepare(priv->clk);
202
203 return 0;
204 }
205
mcp251xfd_reg_invalid(u32 reg)206 static inline bool mcp251xfd_reg_invalid(u32 reg)
207 {
208 return reg == 0x0 || reg == 0xffffffff;
209 }
210
211 static inline int
mcp251xfd_chip_get_mode(const struct mcp251xfd_priv * priv,u8 * mode)212 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
213 {
214 u32 val;
215 int err;
216
217 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
218 if (err)
219 return err;
220
221 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
222
223 return 0;
224 }
225
226 static int
__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req,bool nowait)227 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
228 const u8 mode_req, bool nowait)
229 {
230 const struct can_bittiming *bt = &priv->can.bittiming;
231 unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;
232 u32 con = 0, con_reqop, osc = 0;
233 u8 mode;
234 int err;
235
236 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
237 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
238 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
239 if (err == -EBADMSG) {
240 netdev_err(priv->ndev,
241 "Failed to set Requested Operation Mode.\n");
242
243 return -ENODEV;
244 } else if (err) {
245 return err;
246 }
247
248 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
249 return 0;
250
251 if (bt->bitrate)
252 timeout_us = max_t(unsigned long, timeout_us,
253 MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /
254 bt->bitrate);
255
256 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
257 !mcp251xfd_reg_invalid(con) &&
258 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
259 con) == mode_req,
260 MCP251XFD_POLL_SLEEP_US, timeout_us);
261 if (err != -ETIMEDOUT && err != -EBADMSG)
262 return err;
263
264 /* Ignore return value.
265 * Print below error messages, even if this fails.
266 */
267 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
268
269 if (mcp251xfd_reg_invalid(con)) {
270 netdev_err(priv->ndev,
271 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
272 con, osc);
273
274 return -ENODEV;
275 }
276
277 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
278 netdev_err(priv->ndev,
279 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
280 mcp251xfd_get_mode_str(mode_req), mode_req,
281 mcp251xfd_get_mode_str(mode), mode,
282 con, osc);
283
284 return -ETIMEDOUT;
285 }
286
287 static inline int
mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req)288 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
289 const u8 mode_req)
290 {
291 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
292 }
293
294 static inline int __maybe_unused
mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv * priv,const u8 mode_req)295 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
296 const u8 mode_req)
297 {
298 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
299 }
300
301 static int
mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv * priv,u32 osc_reference,u32 osc_mask)302 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
303 u32 osc_reference, u32 osc_mask)
304 {
305 u32 osc;
306 int err;
307
308 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
309 !mcp251xfd_reg_invalid(osc) &&
310 (osc & osc_mask) == osc_reference,
311 MCP251XFD_OSC_STAB_SLEEP_US,
312 MCP251XFD_OSC_STAB_TIMEOUT_US);
313 if (err != -ETIMEDOUT)
314 return err;
315
316 if (mcp251xfd_reg_invalid(osc)) {
317 netdev_err(priv->ndev,
318 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
319 osc);
320 return -ENODEV;
321 }
322
323 netdev_err(priv->ndev,
324 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
325 mcp251xfd_get_osc_str(osc, osc_reference),
326 osc, osc_reference, osc_mask);
327
328 return -ETIMEDOUT;
329 }
330
mcp251xfd_chip_wake(const struct mcp251xfd_priv * priv)331 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
332 {
333 u32 osc, osc_reference, osc_mask;
334 int err;
335
336 /* For normal sleep on MCP2517FD and MCP2518FD, clearing
337 * "Oscillator Disable" will wake the chip. For low power mode
338 * on MCP2518FD, asserting the chip select will wake the
339 * chip. Writing to the Oscillator register will wake it in
340 * both cases.
341 */
342 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
343 MCP251XFD_REG_OSC_CLKODIV_10);
344
345 /* We cannot check for the PLL ready bit (either set or
346 * unset), as the PLL might be enabled. This can happen if the
347 * system reboots, while the mcp251xfd stays powered.
348 */
349 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
350 osc_mask = MCP251XFD_REG_OSC_OSCRDY;
351
352 /* If the controller is in Sleep Mode the following write only
353 * removes the "Oscillator Disable" bit and powers it up. All
354 * other bits are unaffected.
355 */
356 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
357 if (err)
358 return err;
359
360 /* Sometimes the PLL is stuck enabled, the controller never
361 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
362 * caller takes care of retry.
363 */
364 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
365 }
366
mcp251xfd_chip_sleep(const struct mcp251xfd_priv * priv)367 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
368 {
369 if (priv->pll_enable) {
370 u32 osc;
371 int err;
372
373 /* Turn off PLL */
374 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
375 MCP251XFD_REG_OSC_CLKODIV_10);
376 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
377 if (err)
378 netdev_err(priv->ndev,
379 "Failed to disable PLL.\n");
380
381 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
382 }
383
384 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
385 }
386
mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv * priv)387 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
388 {
389 const __be16 cmd = mcp251xfd_cmd_reset();
390 int err;
391
392 /* The Set Mode and SPI Reset command only works if the
393 * controller is not in Sleep Mode.
394 */
395 err = mcp251xfd_chip_wake(priv);
396 if (err)
397 return err;
398
399 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
400 if (err)
401 return err;
402
403 /* spi_write_then_read() works with non DMA-safe buffers */
404 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
405 }
406
mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv * priv)407 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
408 {
409 u32 osc_reference, osc_mask;
410 u8 mode;
411 int err;
412
413 /* Check for reset defaults of OSC reg.
414 * This will take care of stabilization period.
415 */
416 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
417 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
418 MCP251XFD_REG_OSC_CLKODIV_10);
419 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
420 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
421 if (err)
422 return err;
423
424 err = mcp251xfd_chip_get_mode(priv, &mode);
425 if (err)
426 return err;
427
428 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
429 netdev_info(priv->ndev,
430 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
431 mcp251xfd_get_mode_str(mode), mode);
432 return -ETIMEDOUT;
433 }
434
435 return 0;
436 }
437
mcp251xfd_chip_softreset(const struct mcp251xfd_priv * priv)438 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
439 {
440 int err, i;
441
442 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
443 if (i)
444 netdev_info(priv->ndev,
445 "Retrying to reset controller.\n");
446
447 err = mcp251xfd_chip_softreset_do(priv);
448 if (err == -ETIMEDOUT)
449 continue;
450 if (err)
451 return err;
452
453 err = mcp251xfd_chip_softreset_check(priv);
454 if (err == -ETIMEDOUT)
455 continue;
456 if (err)
457 return err;
458
459 return 0;
460 }
461
462 return err;
463 }
464
mcp251xfd_chip_clock_init(const struct mcp251xfd_priv * priv)465 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
466 {
467 u32 osc, osc_reference, osc_mask;
468 int err;
469
470 /* Activate Low Power Mode on Oscillator Disable. This only
471 * works on the MCP2518FD. The MCP2517FD will go into normal
472 * Sleep Mode instead.
473 */
474 osc = MCP251XFD_REG_OSC_LPMEN |
475 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
476 MCP251XFD_REG_OSC_CLKODIV_10);
477 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
478 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
479
480 if (priv->pll_enable) {
481 osc |= MCP251XFD_REG_OSC_PLLEN;
482 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
483 }
484
485 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
486 if (err)
487 return err;
488
489 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
490 if (err)
491 return err;
492
493 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
494
495 return 0;
496 }
497
mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv * priv)498 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
499 {
500 /* Set Time Base Counter Prescaler to 1.
501 *
502 * This means an overflow of the 32 bit Time Base Counter
503 * register at 40 MHz every 107 seconds.
504 */
505 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
506 MCP251XFD_REG_TSCON_TBCEN);
507 }
508
mcp251xfd_set_bittiming(const struct mcp251xfd_priv * priv)509 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
510 {
511 const struct can_bittiming *bt = &priv->can.bittiming;
512 const struct can_bittiming *dbt = &priv->can.data_bittiming;
513 u32 val = 0;
514 s8 tdco;
515 int err;
516
517 /* CAN Control Register
518 *
519 * - no transmit bandwidth sharing
520 * - config mode
521 * - disable transmit queue
522 * - store in transmit FIFO event
523 * - transition to restricted operation mode on system error
524 * - ESI is transmitted recessive when ESI of message is high or
525 * CAN controller error passive
526 * - restricted retransmission attempts,
527 * use TQXCON_TXAT and FIFOCON_TXAT
528 * - wake-up filter bits T11FILTER
529 * - use CAN bus line filter for wakeup
530 * - protocol exception is treated as a form error
531 * - Do not compare data bytes
532 */
533 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
534 MCP251XFD_REG_CON_MODE_CONFIG) |
535 MCP251XFD_REG_CON_STEF |
536 MCP251XFD_REG_CON_ESIGM |
537 MCP251XFD_REG_CON_RTXAT |
538 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
539 MCP251XFD_REG_CON_WFT_T11FILTER) |
540 MCP251XFD_REG_CON_WAKFIL |
541 MCP251XFD_REG_CON_PXEDIS;
542
543 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
544 val |= MCP251XFD_REG_CON_ISOCRCEN;
545
546 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
547 if (err)
548 return err;
549
550 /* Nominal Bit Time */
551 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
552 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
553 bt->prop_seg + bt->phase_seg1 - 1) |
554 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
555 bt->phase_seg2 - 1) |
556 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
557
558 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
559 if (err)
560 return err;
561
562 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
563 return 0;
564
565 /* Data Bit Time */
566 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
567 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
568 dbt->prop_seg + dbt->phase_seg1 - 1) |
569 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
570 dbt->phase_seg2 - 1) |
571 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
572
573 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
574 if (err)
575 return err;
576
577 /* Transmitter Delay Compensation */
578 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
579 -64, 63);
580 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
581 MCP251XFD_REG_TDC_TDCMOD_AUTO) |
582 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
583
584 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
585 }
586
mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv * priv)587 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
588 {
589 u32 val;
590
591 if (!priv->rx_int)
592 return 0;
593
594 /* Configure GPIOs:
595 * - PIN0: GPIO Input
596 * - PIN1: GPIO Input/RX Interrupt
597 *
598 * PIN1 must be Input, otherwise there is a glitch on the
599 * rx-INT line. It happens between setting the PIN as output
600 * (in the first byte of the SPI transfer) and configuring the
601 * PIN as interrupt (in the last byte of the SPI transfer).
602 */
603 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
604 MCP251XFD_REG_IOCON_TRIS0;
605 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
606 }
607
mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv * priv)608 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
609 {
610 u32 val;
611
612 if (!priv->rx_int)
613 return 0;
614
615 /* Configure GPIOs:
616 * - PIN0: GPIO Input
617 * - PIN1: GPIO Input
618 */
619 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
620 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
621 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
622 }
623
mcp251xfd_chip_ecc_init(struct mcp251xfd_priv * priv)624 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
625 {
626 struct mcp251xfd_ecc *ecc = &priv->ecc;
627 void *ram;
628 u32 val = 0;
629 int err;
630
631 ecc->ecc_stat = 0;
632
633 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
634 val = MCP251XFD_REG_ECCCON_ECCEN;
635
636 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
637 MCP251XFD_REG_ECCCON_ECCEN, val);
638 if (err)
639 return err;
640
641 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
642 if (!ram)
643 return -ENOMEM;
644
645 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
646 MCP251XFD_RAM_SIZE);
647 kfree(ram);
648
649 return err;
650 }
651
mcp251xfd_get_normal_mode(const struct mcp251xfd_priv * priv)652 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
653 {
654 u8 mode;
655
656 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
657 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
658 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
659 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
660 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
661 mode = MCP251XFD_REG_CON_MODE_MIXED;
662 else
663 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
664
665 return mode;
666 }
667
668 static int
__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv,bool nowait)669 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
670 bool nowait)
671 {
672 u8 mode;
673
674 mode = mcp251xfd_get_normal_mode(priv);
675
676 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
677 }
678
679 static inline int
mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv)680 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
681 {
682 return __mcp251xfd_chip_set_normal_mode(priv, false);
683 }
684
685 static inline int
mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv * priv)686 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
687 {
688 return __mcp251xfd_chip_set_normal_mode(priv, true);
689 }
690
mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv * priv)691 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
692 {
693 u32 val;
694 int err;
695
696 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
697 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
698 if (err)
699 return err;
700
701 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
702 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
703 if (err)
704 return err;
705
706 val = MCP251XFD_REG_INT_CERRIE |
707 MCP251XFD_REG_INT_SERRIE |
708 MCP251XFD_REG_INT_RXOVIE |
709 MCP251XFD_REG_INT_TXATIE |
710 MCP251XFD_REG_INT_SPICRCIE |
711 MCP251XFD_REG_INT_ECCIE |
712 MCP251XFD_REG_INT_TEFIE |
713 MCP251XFD_REG_INT_MODIE |
714 MCP251XFD_REG_INT_RXIE;
715
716 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
717 val |= MCP251XFD_REG_INT_IVMIE;
718
719 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
720 }
721
mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv * priv)722 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
723 {
724 int err;
725 u32 mask;
726
727 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
728 if (err)
729 return err;
730
731 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
732 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
733 mask, 0x0);
734 if (err)
735 return err;
736
737 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
738 }
739
mcp251xfd_chip_stop(struct mcp251xfd_priv * priv,const enum can_state state)740 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
741 const enum can_state state)
742 {
743 priv->can.state = state;
744
745 mcp251xfd_chip_interrupts_disable(priv);
746 mcp251xfd_chip_rx_int_disable(priv);
747 mcp251xfd_timestamp_stop(priv);
748 mcp251xfd_chip_sleep(priv);
749 }
750
mcp251xfd_chip_start(struct mcp251xfd_priv * priv)751 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
752 {
753 int err;
754
755 err = mcp251xfd_chip_softreset(priv);
756 if (err)
757 goto out_chip_stop;
758
759 err = mcp251xfd_chip_clock_init(priv);
760 if (err)
761 goto out_chip_stop;
762
763 err = mcp251xfd_chip_timestamp_init(priv);
764 if (err)
765 goto out_chip_stop;
766
767 mcp251xfd_timestamp_start(priv);
768
769 err = mcp251xfd_set_bittiming(priv);
770 if (err)
771 goto out_chip_stop;
772
773 err = mcp251xfd_chip_rx_int_enable(priv);
774 if (err)
775 goto out_chip_stop;
776
777 err = mcp251xfd_chip_ecc_init(priv);
778 if (err)
779 goto out_chip_stop;
780
781 err = mcp251xfd_ring_init(priv);
782 if (err)
783 goto out_chip_stop;
784
785 err = mcp251xfd_chip_fifo_init(priv);
786 if (err)
787 goto out_chip_stop;
788
789 priv->can.state = CAN_STATE_ERROR_ACTIVE;
790
791 err = mcp251xfd_chip_set_normal_mode(priv);
792 if (err)
793 goto out_chip_stop;
794
795 return 0;
796
797 out_chip_stop:
798 mcp251xfd_dump(priv);
799 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
800
801 return err;
802 }
803
mcp251xfd_set_mode(struct net_device * ndev,enum can_mode mode)804 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
805 {
806 struct mcp251xfd_priv *priv = netdev_priv(ndev);
807 int err;
808
809 switch (mode) {
810 case CAN_MODE_START:
811 err = mcp251xfd_chip_start(priv);
812 if (err)
813 return err;
814
815 err = mcp251xfd_chip_interrupts_enable(priv);
816 if (err) {
817 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
818 return err;
819 }
820
821 netif_wake_queue(ndev);
822 break;
823
824 default:
825 return -EOPNOTSUPP;
826 }
827
828 return 0;
829 }
830
__mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)831 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
832 struct can_berr_counter *bec)
833 {
834 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
835 u32 trec;
836 int err;
837
838 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
839 if (err)
840 return err;
841
842 if (trec & MCP251XFD_REG_TREC_TXBO)
843 bec->txerr = 256;
844 else
845 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
846 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
847
848 return 0;
849 }
850
mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)851 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
852 struct can_berr_counter *bec)
853 {
854 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
855
856 /* Avoid waking up the controller if the interface is down */
857 if (!(ndev->flags & IFF_UP))
858 return 0;
859
860 /* The controller is powered down during Bus Off, use saved
861 * bec values.
862 */
863 if (priv->can.state == CAN_STATE_BUS_OFF) {
864 *bec = priv->bec;
865 return 0;
866 }
867
868 return __mcp251xfd_get_berr_counter(ndev, bec);
869 }
870
871 static struct sk_buff *
mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv * priv,struct can_frame ** cf,u32 * ts_raw)872 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
873 struct can_frame **cf, u32 *ts_raw)
874 {
875 struct sk_buff *skb;
876 int err;
877
878 err = mcp251xfd_get_timestamp_raw(priv, ts_raw);
879 if (err)
880 return NULL;
881
882 skb = alloc_can_err_skb(priv->ndev, cf);
883 if (skb)
884 mcp251xfd_skb_set_timestamp_raw(priv, skb, *ts_raw);
885
886 return skb;
887 }
888
mcp251xfd_handle_rxovif(struct mcp251xfd_priv * priv)889 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
890 {
891 struct net_device_stats *stats = &priv->ndev->stats;
892 struct mcp251xfd_rx_ring *ring;
893 struct sk_buff *skb;
894 struct can_frame *cf;
895 u32 ts_raw, rxovif;
896 int err, i;
897
898 stats->rx_over_errors++;
899 stats->rx_errors++;
900
901 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
902 if (err)
903 return err;
904
905 mcp251xfd_for_each_rx_ring(priv, ring, i) {
906 if (!(rxovif & BIT(ring->fifo_nr)))
907 continue;
908
909 /* If SERRIF is active, there was a RX MAB overflow. */
910 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
911 if (net_ratelimit())
912 netdev_dbg(priv->ndev,
913 "RX-%d: MAB overflow detected.\n",
914 ring->nr);
915 } else {
916 if (net_ratelimit())
917 netdev_dbg(priv->ndev,
918 "RX-%d: FIFO overflow.\n",
919 ring->nr);
920 }
921
922 err = regmap_update_bits(priv->map_reg,
923 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
924 MCP251XFD_REG_FIFOSTA_RXOVIF,
925 0x0);
926 if (err)
927 return err;
928 }
929
930 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
931 if (!skb)
932 return 0;
933
934 cf->can_id |= CAN_ERR_CRTL;
935 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
936
937 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
938 if (err)
939 stats->rx_fifo_errors++;
940
941 return 0;
942 }
943
mcp251xfd_handle_txatif(struct mcp251xfd_priv * priv)944 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
945 {
946 netdev_info(priv->ndev, "%s\n", __func__);
947
948 return 0;
949 }
950
mcp251xfd_handle_ivmif(struct mcp251xfd_priv * priv)951 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
952 {
953 struct net_device_stats *stats = &priv->ndev->stats;
954 u32 bdiag1, ts_raw;
955 struct sk_buff *skb;
956 struct can_frame *cf = NULL;
957 int err;
958
959 err = mcp251xfd_get_timestamp_raw(priv, &ts_raw);
960 if (err)
961 return err;
962
963 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
964 if (err)
965 return err;
966
967 /* Write 0s to clear error bits, don't write 1s to non active
968 * bits, as they will be set.
969 */
970 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
971 if (err)
972 return err;
973
974 priv->can.can_stats.bus_error++;
975
976 skb = alloc_can_err_skb(priv->ndev, &cf);
977 if (cf)
978 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
979
980 /* Controller misconfiguration */
981 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
982 netdev_err(priv->ndev,
983 "recv'd DLC is larger than PLSIZE of FIFO element.");
984
985 /* RX errors */
986 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
987 MCP251XFD_REG_BDIAG1_NCRCERR)) {
988 netdev_dbg(priv->ndev, "CRC error\n");
989
990 stats->rx_errors++;
991 if (cf)
992 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
993 }
994 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
995 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
996 netdev_dbg(priv->ndev, "Stuff error\n");
997
998 stats->rx_errors++;
999 if (cf)
1000 cf->data[2] |= CAN_ERR_PROT_STUFF;
1001 }
1002 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1003 MCP251XFD_REG_BDIAG1_NFORMERR)) {
1004 netdev_dbg(priv->ndev, "Format error\n");
1005
1006 stats->rx_errors++;
1007 if (cf)
1008 cf->data[2] |= CAN_ERR_PROT_FORM;
1009 }
1010
1011 /* TX errors */
1012 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1013 netdev_dbg(priv->ndev, "NACK error\n");
1014
1015 stats->tx_errors++;
1016 if (cf) {
1017 cf->can_id |= CAN_ERR_ACK;
1018 cf->data[2] |= CAN_ERR_PROT_TX;
1019 }
1020 }
1021 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1022 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1023 netdev_dbg(priv->ndev, "Bit1 error\n");
1024
1025 stats->tx_errors++;
1026 if (cf)
1027 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1028 }
1029 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1030 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1031 netdev_dbg(priv->ndev, "Bit0 error\n");
1032
1033 stats->tx_errors++;
1034 if (cf)
1035 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1036 }
1037
1038 if (!cf)
1039 return 0;
1040
1041 mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw);
1042 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1043 if (err)
1044 stats->rx_fifo_errors++;
1045
1046 return 0;
1047 }
1048
mcp251xfd_handle_cerrif(struct mcp251xfd_priv * priv)1049 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1050 {
1051 struct net_device_stats *stats = &priv->ndev->stats;
1052 struct sk_buff *skb;
1053 struct can_frame *cf = NULL;
1054 enum can_state new_state, rx_state, tx_state;
1055 u32 trec, ts_raw;
1056 int err;
1057
1058 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1059 if (err)
1060 return err;
1061
1062 if (trec & MCP251XFD_REG_TREC_TXBO)
1063 tx_state = CAN_STATE_BUS_OFF;
1064 else if (trec & MCP251XFD_REG_TREC_TXBP)
1065 tx_state = CAN_STATE_ERROR_PASSIVE;
1066 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1067 tx_state = CAN_STATE_ERROR_WARNING;
1068 else
1069 tx_state = CAN_STATE_ERROR_ACTIVE;
1070
1071 if (trec & MCP251XFD_REG_TREC_RXBP)
1072 rx_state = CAN_STATE_ERROR_PASSIVE;
1073 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1074 rx_state = CAN_STATE_ERROR_WARNING;
1075 else
1076 rx_state = CAN_STATE_ERROR_ACTIVE;
1077
1078 new_state = max(tx_state, rx_state);
1079 if (new_state == priv->can.state)
1080 return 0;
1081
1082 /* The skb allocation might fail, but can_change_state()
1083 * handles cf == NULL.
1084 */
1085 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
1086 can_change_state(priv->ndev, cf, tx_state, rx_state);
1087
1088 if (new_state == CAN_STATE_BUS_OFF) {
1089 /* As we're going to switch off the chip now, let's
1090 * save the error counters and return them to
1091 * userspace, if do_get_berr_counter() is called while
1092 * the chip is in Bus Off.
1093 */
1094 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1095 if (err)
1096 return err;
1097
1098 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1099 can_bus_off(priv->ndev);
1100 }
1101
1102 if (!skb)
1103 return 0;
1104
1105 if (new_state != CAN_STATE_BUS_OFF) {
1106 struct can_berr_counter bec;
1107
1108 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1109 if (err)
1110 return err;
1111 cf->can_id |= CAN_ERR_CNT;
1112 cf->data[6] = bec.txerr;
1113 cf->data[7] = bec.rxerr;
1114 }
1115
1116 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1117 if (err)
1118 stats->rx_fifo_errors++;
1119
1120 return 0;
1121 }
1122
1123 static int
mcp251xfd_handle_modif(const struct mcp251xfd_priv * priv,bool * set_normal_mode)1124 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1125 {
1126 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1127 u8 mode;
1128 int err;
1129
1130 err = mcp251xfd_chip_get_mode(priv, &mode);
1131 if (err)
1132 return err;
1133
1134 if (mode == mode_reference) {
1135 netdev_dbg(priv->ndev,
1136 "Controller changed into %s Mode (%u).\n",
1137 mcp251xfd_get_mode_str(mode), mode);
1138 return 0;
1139 }
1140
1141 /* According to MCP2517FD errata DS80000792B 1., during a TX
1142 * MAB underflow, the controller will transition to Restricted
1143 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1144 *
1145 * However this is not always the case. If SERR2LOM is
1146 * configured for Restricted Operation Mode (SERR2LOM not set)
1147 * the MCP2517FD will sometimes transition to Listen Only Mode
1148 * first. When polling this bit we see that it will transition
1149 * to Restricted Operation Mode shortly after.
1150 */
1151 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1152 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1153 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1154 netdev_dbg(priv->ndev,
1155 "Controller changed into %s Mode (%u).\n",
1156 mcp251xfd_get_mode_str(mode), mode);
1157 else
1158 netdev_err(priv->ndev,
1159 "Controller changed into %s Mode (%u).\n",
1160 mcp251xfd_get_mode_str(mode), mode);
1161
1162 /* After the application requests Normal mode, the controller
1163 * will automatically attempt to retransmit the message that
1164 * caused the TX MAB underflow.
1165 *
1166 * However, if there is an ECC error in the TX-RAM, we first
1167 * have to reload the tx-object before requesting Normal
1168 * mode. This is done later in mcp251xfd_handle_eccif().
1169 */
1170 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1171 *set_normal_mode = true;
1172 return 0;
1173 }
1174
1175 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1176 }
1177
mcp251xfd_handle_serrif(struct mcp251xfd_priv * priv)1178 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1179 {
1180 struct mcp251xfd_ecc *ecc = &priv->ecc;
1181 struct net_device_stats *stats = &priv->ndev->stats;
1182 bool handled = false;
1183
1184 /* TX MAB underflow
1185 *
1186 * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1187 * underflow is indicated by SERRIF and MODIF.
1188 *
1189 * In addition to the effects mentioned in the Errata, there
1190 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1191 * will be seen as well.
1192 *
1193 * Sometimes there is an ECC error in the TX-RAM, which leads
1194 * to a TX MAB underflow.
1195 *
1196 * However, probably due to a race condition, there is no
1197 * associated MODIF pending.
1198 *
1199 * Further, there are situations, where the SERRIF is caused
1200 * by an ECC error in the TX-RAM, but not even the ECCIF is
1201 * set. This only seems to happen _after_ the first occurrence
1202 * of a ECCIF (which is tracked in ecc->cnt).
1203 *
1204 * Treat all as a known system errors..
1205 */
1206 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1207 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1208 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1209 ecc->cnt) {
1210 const char *msg;
1211
1212 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1213 ecc->cnt)
1214 msg = "TX MAB underflow due to ECC error detected.";
1215 else
1216 msg = "TX MAB underflow detected.";
1217
1218 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1219 netdev_dbg(priv->ndev, "%s\n", msg);
1220 else
1221 netdev_info(priv->ndev, "%s\n", msg);
1222
1223 stats->tx_aborted_errors++;
1224 stats->tx_errors++;
1225 handled = true;
1226 }
1227
1228 /* RX MAB overflow
1229 *
1230 * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1231 * overflow is indicated by SERRIF.
1232 *
1233 * In addition to the effects mentioned in the Errata, (most
1234 * of the times) a RXOVIF is raised, if the FIFO that is being
1235 * received into has the RXOVIE activated (and we have enabled
1236 * RXOVIE on all FIFOs).
1237 *
1238 * Sometimes there is no RXOVIF just a RXIF is pending.
1239 *
1240 * Treat all as a known system errors..
1241 */
1242 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1243 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1244 stats->rx_dropped++;
1245 handled = true;
1246 }
1247
1248 if (!handled)
1249 netdev_err(priv->ndev,
1250 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1251 priv->regs_status.intf);
1252
1253 return 0;
1254 }
1255
1256 static int
mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv * priv,u8 nr)1257 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1258 {
1259 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1260 struct mcp251xfd_ecc *ecc = &priv->ecc;
1261 struct mcp251xfd_tx_obj *tx_obj;
1262 u8 chip_tx_tail, tx_tail, offset;
1263 u16 addr;
1264 int err;
1265
1266 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1267
1268 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1269 if (err)
1270 return err;
1271
1272 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1273 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1274
1275 /* Bail out if one of the following is met:
1276 * - tx_tail information is inconsistent
1277 * - for mcp2517fd: offset not 0
1278 * - for mcp2518fd: offset not 0 or 1
1279 */
1280 if (chip_tx_tail != tx_tail ||
1281 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1282 mcp251xfd_is_251863(priv))))) {
1283 netdev_err(priv->ndev,
1284 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1285 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1286 offset);
1287 return -EINVAL;
1288 }
1289
1290 netdev_info(priv->ndev,
1291 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1292 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1293 "Single" : "Double",
1294 addr, nr, tx_ring->tail, tx_tail, offset);
1295
1296 /* reload tx_obj into controller RAM ... */
1297 tx_obj = &tx_ring->obj[nr];
1298 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1299 if (err)
1300 return err;
1301
1302 /* ... and trigger retransmit */
1303 return mcp251xfd_chip_set_normal_mode(priv);
1304 }
1305
1306 static int
mcp251xfd_handle_eccif(struct mcp251xfd_priv * priv,bool set_normal_mode)1307 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1308 {
1309 struct mcp251xfd_ecc *ecc = &priv->ecc;
1310 const char *msg;
1311 bool in_tx_ram;
1312 u32 ecc_stat;
1313 u16 addr;
1314 u8 nr;
1315 int err;
1316
1317 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1318 if (err)
1319 return err;
1320
1321 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1322 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1323 if (err)
1324 return err;
1325
1326 /* Check if ECC error occurred in TX-RAM */
1327 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1328 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1329 if (!err)
1330 in_tx_ram = true;
1331 else if (err == -ENOENT)
1332 in_tx_ram = false;
1333 else
1334 return err;
1335
1336 /* Errata Reference:
1337 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1338 *
1339 * ECC single error correction does not work in all cases:
1340 *
1341 * Fix/Work Around:
1342 * Enable single error correction and double error detection
1343 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1344 * detection interrupt and do not rely on the error
1345 * correction. Instead, handle both interrupts as a
1346 * notification that the RAM word at ERRADDR was corrupted.
1347 */
1348 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1349 msg = "Single ECC Error detected at address";
1350 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1351 msg = "Double ECC Error detected at address";
1352 else
1353 return -EINVAL;
1354
1355 if (!in_tx_ram) {
1356 ecc->ecc_stat = 0;
1357
1358 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1359 } else {
1360 /* Re-occurring error? */
1361 if (ecc->ecc_stat == ecc_stat) {
1362 ecc->cnt++;
1363 } else {
1364 ecc->ecc_stat = ecc_stat;
1365 ecc->cnt = 1;
1366 }
1367
1368 netdev_info(priv->ndev,
1369 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1370 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1371
1372 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1373 return mcp251xfd_handle_eccif_recover(priv, nr);
1374 }
1375
1376 if (set_normal_mode)
1377 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1378
1379 return 0;
1380 }
1381
mcp251xfd_handle_spicrcif(struct mcp251xfd_priv * priv)1382 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1383 {
1384 int err;
1385 u32 crc;
1386
1387 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1388 if (err)
1389 return err;
1390
1391 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1392 MCP251XFD_REG_CRC_IF_MASK,
1393 ~crc);
1394 if (err)
1395 return err;
1396
1397 if (crc & MCP251XFD_REG_CRC_FERRIF)
1398 netdev_notice(priv->ndev, "CRC write command format error.\n");
1399 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1400 netdev_notice(priv->ndev,
1401 "CRC write error detected. CRC=0x%04lx.\n",
1402 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1403
1404 return 0;
1405 }
1406
mcp251xfd_read_regs_status(struct mcp251xfd_priv * priv)1407 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1408 {
1409 const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1410 size_t len;
1411
1412 if (priv->rx_ring_num == 1)
1413 len = sizeof(priv->regs_status.intf);
1414 else
1415 len = sizeof(priv->regs_status);
1416
1417 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1418 &priv->regs_status, len / val_bytes);
1419 }
1420
1421 #define mcp251xfd_handle(priv, irq, ...) \
1422 ({ \
1423 struct mcp251xfd_priv *_priv = (priv); \
1424 int err; \
1425 \
1426 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1427 if (err) \
1428 netdev_err(_priv->ndev, \
1429 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1430 __stringify(irq), err); \
1431 err; \
1432 })
1433
mcp251xfd_irq(int irq,void * dev_id)1434 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1435 {
1436 struct mcp251xfd_priv *priv = dev_id;
1437 irqreturn_t handled = IRQ_NONE;
1438 int err;
1439
1440 if (priv->rx_int)
1441 do {
1442 int rx_pending;
1443
1444 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1445 if (!rx_pending)
1446 break;
1447
1448 /* Assume 1st RX-FIFO pending, if other FIFOs
1449 * are pending the main IRQ handler will take
1450 * care.
1451 */
1452 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1453 err = mcp251xfd_handle(priv, rxif);
1454 if (err)
1455 goto out_fail;
1456
1457 handled = IRQ_HANDLED;
1458
1459 /* We don't know which RX-FIFO is pending, but only
1460 * handle the 1st RX-FIFO. Leave loop here if we have
1461 * more than 1 RX-FIFO to avoid starvation.
1462 */
1463 } while (priv->rx_ring_num == 1);
1464
1465 do {
1466 u32 intf_pending, intf_pending_clearable;
1467 bool set_normal_mode = false;
1468
1469 err = mcp251xfd_read_regs_status(priv);
1470 if (err)
1471 goto out_fail;
1472
1473 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1474 priv->regs_status.intf) &
1475 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1476 priv->regs_status.intf);
1477
1478 if (!(intf_pending)) {
1479 can_rx_offload_threaded_irq_finish(&priv->offload);
1480 return handled;
1481 }
1482
1483 /* Some interrupts must be ACKed in the
1484 * MCP251XFD_REG_INT register.
1485 * - First ACK then handle, to avoid lost-IRQ race
1486 * condition on fast re-occurring interrupts.
1487 * - Write "0" to clear active IRQs, "1" to all other,
1488 * to avoid r/m/w race condition on the
1489 * MCP251XFD_REG_INT register.
1490 */
1491 intf_pending_clearable = intf_pending &
1492 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1493 if (intf_pending_clearable) {
1494 err = regmap_update_bits(priv->map_reg,
1495 MCP251XFD_REG_INT,
1496 MCP251XFD_REG_INT_IF_MASK,
1497 ~intf_pending_clearable);
1498 if (err)
1499 goto out_fail;
1500 }
1501
1502 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1503 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1504 if (err)
1505 goto out_fail;
1506 }
1507
1508 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1509 err = mcp251xfd_handle(priv, rxif);
1510 if (err)
1511 goto out_fail;
1512 }
1513
1514 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1515 err = mcp251xfd_handle(priv, tefif);
1516 if (err)
1517 goto out_fail;
1518 }
1519
1520 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1521 err = mcp251xfd_handle(priv, rxovif);
1522 if (err)
1523 goto out_fail;
1524 }
1525
1526 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1527 err = mcp251xfd_handle(priv, txatif);
1528 if (err)
1529 goto out_fail;
1530 }
1531
1532 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1533 err = mcp251xfd_handle(priv, ivmif);
1534 if (err)
1535 goto out_fail;
1536 }
1537
1538 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1539 err = mcp251xfd_handle(priv, serrif);
1540 if (err)
1541 goto out_fail;
1542 }
1543
1544 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1545 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1546 if (err)
1547 goto out_fail;
1548 }
1549
1550 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1551 err = mcp251xfd_handle(priv, spicrcif);
1552 if (err)
1553 goto out_fail;
1554 }
1555
1556 /* On the MCP2527FD and MCP2518FD, we don't get a
1557 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1558 * ERROR_ACTIVE.
1559 */
1560 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1561 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1562 err = mcp251xfd_handle(priv, cerrif);
1563 if (err)
1564 goto out_fail;
1565
1566 /* In Bus Off we completely shut down the
1567 * controller. Every subsequent register read
1568 * will read bogus data, and if
1569 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1570 * check will fail, too. So leave IRQ handler
1571 * directly.
1572 */
1573 if (priv->can.state == CAN_STATE_BUS_OFF) {
1574 can_rx_offload_threaded_irq_finish(&priv->offload);
1575 return IRQ_HANDLED;
1576 }
1577 }
1578
1579 handled = IRQ_HANDLED;
1580 } while (1);
1581
1582 out_fail:
1583 can_rx_offload_threaded_irq_finish(&priv->offload);
1584
1585 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1586 err, priv->regs_status.intf);
1587 mcp251xfd_dump(priv);
1588 mcp251xfd_chip_interrupts_disable(priv);
1589 mcp251xfd_timestamp_stop(priv);
1590
1591 return handled;
1592 }
1593
mcp251xfd_open(struct net_device * ndev)1594 static int mcp251xfd_open(struct net_device *ndev)
1595 {
1596 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1597 const struct spi_device *spi = priv->spi;
1598 int err;
1599
1600 err = open_candev(ndev);
1601 if (err)
1602 return err;
1603
1604 err = pm_runtime_resume_and_get(ndev->dev.parent);
1605 if (err)
1606 goto out_close_candev;
1607
1608 err = mcp251xfd_ring_alloc(priv);
1609 if (err)
1610 goto out_pm_runtime_put;
1611
1612 err = mcp251xfd_transceiver_enable(priv);
1613 if (err)
1614 goto out_mcp251xfd_ring_free;
1615
1616 mcp251xfd_timestamp_init(priv);
1617
1618 err = mcp251xfd_chip_start(priv);
1619 if (err)
1620 goto out_transceiver_disable;
1621
1622 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1623 can_rx_offload_enable(&priv->offload);
1624
1625 priv->wq = alloc_ordered_workqueue("%s-mcp251xfd_wq",
1626 WQ_FREEZABLE | WQ_MEM_RECLAIM,
1627 dev_name(&spi->dev));
1628 if (!priv->wq) {
1629 err = -ENOMEM;
1630 goto out_can_rx_offload_disable;
1631 }
1632 INIT_WORK(&priv->tx_work, mcp251xfd_tx_obj_write_sync);
1633
1634 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1635 IRQF_SHARED | IRQF_ONESHOT,
1636 dev_name(&spi->dev), priv);
1637 if (err)
1638 goto out_destroy_workqueue;
1639
1640 err = mcp251xfd_chip_interrupts_enable(priv);
1641 if (err)
1642 goto out_free_irq;
1643
1644 netif_start_queue(ndev);
1645
1646 return 0;
1647
1648 out_free_irq:
1649 free_irq(spi->irq, priv);
1650 out_destroy_workqueue:
1651 destroy_workqueue(priv->wq);
1652 out_can_rx_offload_disable:
1653 can_rx_offload_disable(&priv->offload);
1654 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1655 out_transceiver_disable:
1656 mcp251xfd_transceiver_disable(priv);
1657 out_mcp251xfd_ring_free:
1658 mcp251xfd_ring_free(priv);
1659 out_pm_runtime_put:
1660 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1661 pm_runtime_put(ndev->dev.parent);
1662 out_close_candev:
1663 close_candev(ndev);
1664
1665 return err;
1666 }
1667
mcp251xfd_stop(struct net_device * ndev)1668 static int mcp251xfd_stop(struct net_device *ndev)
1669 {
1670 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1671
1672 netif_stop_queue(ndev);
1673 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1674 hrtimer_cancel(&priv->rx_irq_timer);
1675 hrtimer_cancel(&priv->tx_irq_timer);
1676 mcp251xfd_chip_interrupts_disable(priv);
1677 free_irq(ndev->irq, priv);
1678 destroy_workqueue(priv->wq);
1679 can_rx_offload_disable(&priv->offload);
1680 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1681 mcp251xfd_transceiver_disable(priv);
1682 mcp251xfd_ring_free(priv);
1683 close_candev(ndev);
1684
1685 pm_runtime_put(ndev->dev.parent);
1686
1687 return 0;
1688 }
1689
1690 static const struct net_device_ops mcp251xfd_netdev_ops = {
1691 .ndo_open = mcp251xfd_open,
1692 .ndo_stop = mcp251xfd_stop,
1693 .ndo_start_xmit = mcp251xfd_start_xmit,
1694 .ndo_eth_ioctl = can_eth_ioctl_hwts,
1695 .ndo_change_mtu = can_change_mtu,
1696 };
1697
1698 static void
mcp251xfd_register_quirks(struct mcp251xfd_priv * priv)1699 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1700 {
1701 const struct spi_device *spi = priv->spi;
1702 const struct spi_controller *ctlr = spi->controller;
1703
1704 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1705 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1706 }
1707
mcp251xfd_register_chip_detect(struct mcp251xfd_priv * priv)1708 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1709 {
1710 const struct net_device *ndev = priv->ndev;
1711 const struct mcp251xfd_devtype_data *devtype_data;
1712 u32 osc;
1713 int err;
1714
1715 /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1716 * so use it to autodetect the model.
1717 */
1718 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1719 MCP251XFD_REG_OSC_LPMEN,
1720 MCP251XFD_REG_OSC_LPMEN);
1721 if (err)
1722 return err;
1723
1724 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1725 if (err)
1726 return err;
1727
1728 if (osc & MCP251XFD_REG_OSC_LPMEN) {
1729 /* We cannot distinguish between MCP2518FD and
1730 * MCP251863. If firmware specifies MCP251863, keep
1731 * it, otherwise set to MCP2518FD.
1732 */
1733 if (mcp251xfd_is_251863(priv))
1734 devtype_data = &mcp251xfd_devtype_data_mcp251863;
1735 else
1736 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1737 } else {
1738 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1739 }
1740
1741 if (!mcp251xfd_is_251XFD(priv) &&
1742 priv->devtype_data.model != devtype_data->model) {
1743 netdev_info(ndev,
1744 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1745 __mcp251xfd_get_model_str(devtype_data->model),
1746 mcp251xfd_get_model_str(priv));
1747 }
1748 priv->devtype_data = *devtype_data;
1749
1750 /* We need to preserve the Half Duplex Quirk. */
1751 mcp251xfd_register_quirks(priv);
1752
1753 /* Re-init regmap with quirks of detected model. */
1754 return mcp251xfd_regmap_init(priv);
1755 }
1756
mcp251xfd_register_check_rx_int(struct mcp251xfd_priv * priv)1757 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1758 {
1759 int err, rx_pending;
1760
1761 if (!priv->rx_int)
1762 return 0;
1763
1764 err = mcp251xfd_chip_rx_int_enable(priv);
1765 if (err)
1766 return err;
1767
1768 /* Check if RX_INT is properly working. The RX_INT should not
1769 * be active after a softreset.
1770 */
1771 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1772
1773 err = mcp251xfd_chip_rx_int_disable(priv);
1774 if (err)
1775 return err;
1776
1777 if (!rx_pending)
1778 return 0;
1779
1780 netdev_info(priv->ndev,
1781 "RX_INT active after softreset, disabling RX_INT support.\n");
1782 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1783 priv->rx_int = NULL;
1784
1785 return 0;
1786 }
1787
1788 static int
mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv * priv,u32 * dev_id,u32 * effective_speed_hz_slow,u32 * effective_speed_hz_fast)1789 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1790 u32 *effective_speed_hz_slow,
1791 u32 *effective_speed_hz_fast)
1792 {
1793 struct mcp251xfd_map_buf_nocrc *buf_rx;
1794 struct mcp251xfd_map_buf_nocrc *buf_tx;
1795 struct spi_transfer xfer[2] = { };
1796 int err;
1797
1798 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1799 if (!buf_rx)
1800 return -ENOMEM;
1801
1802 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1803 if (!buf_tx) {
1804 err = -ENOMEM;
1805 goto out_kfree_buf_rx;
1806 }
1807
1808 xfer[0].tx_buf = buf_tx;
1809 xfer[0].len = sizeof(buf_tx->cmd);
1810 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1811 xfer[1].rx_buf = buf_rx->data;
1812 xfer[1].len = sizeof(*dev_id);
1813 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1814
1815 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1816
1817 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1818 if (err)
1819 goto out_kfree_buf_tx;
1820
1821 *dev_id = get_unaligned_le32(buf_rx->data);
1822 *effective_speed_hz_slow = xfer[0].effective_speed_hz;
1823 *effective_speed_hz_fast = xfer[1].effective_speed_hz;
1824
1825 out_kfree_buf_tx:
1826 kfree(buf_tx);
1827 out_kfree_buf_rx:
1828 kfree(buf_rx);
1829
1830 return err;
1831 }
1832
1833 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
1834 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1835
1836 static int
mcp251xfd_register_done(const struct mcp251xfd_priv * priv)1837 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1838 {
1839 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1840 unsigned long clk_rate;
1841 int err;
1842
1843 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1844 &effective_speed_hz_slow,
1845 &effective_speed_hz_fast);
1846 if (err)
1847 return err;
1848
1849 clk_rate = clk_get_rate(priv->clk);
1850
1851 netdev_info(priv->ndev,
1852 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1853 mcp251xfd_get_model_str(priv),
1854 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1855 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1856 priv->rx_int ? '+' : '-',
1857 priv->pll_enable ? '+' : '-',
1858 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1859 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1860 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1861 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1862 MCP251XFD_QUIRK_ACTIVE(ECC),
1863 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1864 clk_rate / 1000000,
1865 clk_rate % 1000000 / 1000 / 10,
1866 priv->can.clock.freq / 1000000,
1867 priv->can.clock.freq % 1000000 / 1000 / 10,
1868 priv->spi_max_speed_hz_orig / 1000000,
1869 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1870 priv->spi_max_speed_hz_slow / 1000000,
1871 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1872 effective_speed_hz_slow / 1000000,
1873 effective_speed_hz_slow % 1000000 / 1000 / 10,
1874 priv->spi_max_speed_hz_fast / 1000000,
1875 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1876 effective_speed_hz_fast / 1000000,
1877 effective_speed_hz_fast % 1000000 / 1000 / 10);
1878
1879 return 0;
1880 }
1881
mcp251xfd_register(struct mcp251xfd_priv * priv)1882 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1883 {
1884 struct net_device *ndev = priv->ndev;
1885 int err;
1886
1887 err = mcp251xfd_clks_and_vdd_enable(priv);
1888 if (err)
1889 return err;
1890
1891 pm_runtime_get_noresume(ndev->dev.parent);
1892 err = pm_runtime_set_active(ndev->dev.parent);
1893 if (err)
1894 goto out_runtime_put_noidle;
1895 pm_runtime_enable(ndev->dev.parent);
1896
1897 mcp251xfd_register_quirks(priv);
1898
1899 err = mcp251xfd_chip_softreset(priv);
1900 if (err == -ENODEV)
1901 goto out_runtime_disable;
1902 if (err)
1903 goto out_chip_sleep;
1904
1905 err = mcp251xfd_chip_clock_init(priv);
1906 if (err == -ENODEV)
1907 goto out_runtime_disable;
1908 if (err)
1909 goto out_chip_sleep;
1910
1911 err = mcp251xfd_register_chip_detect(priv);
1912 if (err)
1913 goto out_chip_sleep;
1914
1915 err = mcp251xfd_register_check_rx_int(priv);
1916 if (err)
1917 goto out_chip_sleep;
1918
1919 mcp251xfd_ethtool_init(priv);
1920
1921 err = register_candev(ndev);
1922 if (err)
1923 goto out_chip_sleep;
1924
1925 err = mcp251xfd_register_done(priv);
1926 if (err)
1927 goto out_unregister_candev;
1928
1929 /* Put controller into sleep mode and let pm_runtime_put()
1930 * disable the clocks and vdd. If CONFIG_PM is not enabled,
1931 * the clocks and vdd will stay powered.
1932 */
1933 err = mcp251xfd_chip_sleep(priv);
1934 if (err)
1935 goto out_unregister_candev;
1936
1937 pm_runtime_put(ndev->dev.parent);
1938
1939 return 0;
1940
1941 out_unregister_candev:
1942 unregister_candev(ndev);
1943 out_chip_sleep:
1944 mcp251xfd_chip_sleep(priv);
1945 out_runtime_disable:
1946 pm_runtime_disable(ndev->dev.parent);
1947 out_runtime_put_noidle:
1948 pm_runtime_put_noidle(ndev->dev.parent);
1949 mcp251xfd_clks_and_vdd_disable(priv);
1950
1951 return err;
1952 }
1953
mcp251xfd_unregister(struct mcp251xfd_priv * priv)1954 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1955 {
1956 struct net_device *ndev = priv->ndev;
1957
1958 unregister_candev(ndev);
1959
1960 if (pm_runtime_enabled(ndev->dev.parent))
1961 pm_runtime_disable(ndev->dev.parent);
1962 else
1963 mcp251xfd_clks_and_vdd_disable(priv);
1964 }
1965
1966 static const struct of_device_id mcp251xfd_of_match[] = {
1967 {
1968 .compatible = "microchip,mcp2517fd",
1969 .data = &mcp251xfd_devtype_data_mcp2517fd,
1970 }, {
1971 .compatible = "microchip,mcp2518fd",
1972 .data = &mcp251xfd_devtype_data_mcp2518fd,
1973 }, {
1974 .compatible = "microchip,mcp251863",
1975 .data = &mcp251xfd_devtype_data_mcp251863,
1976 }, {
1977 .compatible = "microchip,mcp251xfd",
1978 .data = &mcp251xfd_devtype_data_mcp251xfd,
1979 }, {
1980 /* sentinel */
1981 },
1982 };
1983 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
1984
1985 static const struct spi_device_id mcp251xfd_id_table[] = {
1986 {
1987 .name = "mcp2517fd",
1988 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
1989 }, {
1990 .name = "mcp2518fd",
1991 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
1992 }, {
1993 .name = "mcp251863",
1994 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
1995 }, {
1996 .name = "mcp251xfd",
1997 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
1998 }, {
1999 /* sentinel */
2000 },
2001 };
2002 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
2003
mcp251xfd_probe(struct spi_device * spi)2004 static int mcp251xfd_probe(struct spi_device *spi)
2005 {
2006 const void *match;
2007 struct net_device *ndev;
2008 struct mcp251xfd_priv *priv;
2009 struct gpio_desc *rx_int;
2010 struct regulator *reg_vdd, *reg_xceiver;
2011 struct clk *clk;
2012 bool pll_enable = false;
2013 u32 freq = 0;
2014 int err;
2015
2016 if (!spi->irq)
2017 return dev_err_probe(&spi->dev, -ENXIO,
2018 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
2019
2020 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2021 GPIOD_IN);
2022 if (IS_ERR(rx_int))
2023 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2024 "Failed to get RX-INT!\n");
2025
2026 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2027 if (PTR_ERR(reg_vdd) == -ENODEV)
2028 reg_vdd = NULL;
2029 else if (IS_ERR(reg_vdd))
2030 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2031 "Failed to get VDD regulator!\n");
2032
2033 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2034 if (PTR_ERR(reg_xceiver) == -ENODEV)
2035 reg_xceiver = NULL;
2036 else if (IS_ERR(reg_xceiver))
2037 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2038 "Failed to get Transceiver regulator!\n");
2039
2040 clk = devm_clk_get_optional(&spi->dev, NULL);
2041 if (IS_ERR(clk))
2042 return dev_err_probe(&spi->dev, PTR_ERR(clk),
2043 "Failed to get Oscillator (clock)!\n");
2044 if (clk) {
2045 freq = clk_get_rate(clk);
2046 } else {
2047 err = device_property_read_u32(&spi->dev, "clock-frequency",
2048 &freq);
2049 if (err)
2050 return dev_err_probe(&spi->dev, err,
2051 "Failed to get clock-frequency!\n");
2052 }
2053
2054 /* Sanity check */
2055 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2056 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2057 dev_err(&spi->dev,
2058 "Oscillator frequency (%u Hz) is too low or high.\n",
2059 freq);
2060 return -ERANGE;
2061 }
2062
2063 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2064 pll_enable = true;
2065
2066 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2067 MCP251XFD_TX_OBJ_NUM_MAX);
2068 if (!ndev)
2069 return -ENOMEM;
2070
2071 SET_NETDEV_DEV(ndev, &spi->dev);
2072
2073 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2074 ndev->irq = spi->irq;
2075 ndev->flags |= IFF_ECHO;
2076
2077 priv = netdev_priv(ndev);
2078 spi_set_drvdata(spi, priv);
2079 priv->can.clock.freq = freq;
2080 if (pll_enable)
2081 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2082 priv->can.do_set_mode = mcp251xfd_set_mode;
2083 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2084 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2085 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2086 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2087 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2088 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2089 CAN_CTRLMODE_CC_LEN8_DLC;
2090 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2091 priv->ndev = ndev;
2092 priv->spi = spi;
2093 priv->rx_int = rx_int;
2094 priv->clk = clk;
2095 priv->pll_enable = pll_enable;
2096 priv->reg_vdd = reg_vdd;
2097 priv->reg_xceiver = reg_xceiver;
2098
2099 match = device_get_match_data(&spi->dev);
2100 if (match)
2101 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2102 else
2103 priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2104 spi_get_device_id(spi)->driver_data;
2105
2106 /* Errata Reference:
2107 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4.
2108 *
2109 * The SPI can write corrupted data to the RAM at fast SPI
2110 * speeds:
2111 *
2112 * Simultaneous activity on the CAN bus while writing data to
2113 * RAM via the SPI interface, with high SCK frequency, can
2114 * lead to corrupted data being written to RAM.
2115 *
2116 * Fix/Work Around:
2117 * Ensure that FSCK is less than or equal to 0.85 *
2118 * (FSYSCLK/2).
2119 *
2120 * Known good combinations are:
2121 *
2122 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2123 *
2124 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2125 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2126 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2127 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2128 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2129 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2130 *
2131 */
2132 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2133 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2134 freq / 2 / 1000 * 850);
2135 if (priv->pll_enable)
2136 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2137 freq *
2138 MCP251XFD_OSC_PLL_MULTIPLIER /
2139 2 / 1000 * 850);
2140 else
2141 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2142 spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2143 spi->bits_per_word = 8;
2144 spi->rt = true;
2145 err = spi_setup(spi);
2146 if (err)
2147 goto out_free_candev;
2148
2149 err = mcp251xfd_regmap_init(priv);
2150 if (err)
2151 goto out_free_candev;
2152
2153 err = can_rx_offload_add_manual(ndev, &priv->offload,
2154 MCP251XFD_NAPI_WEIGHT);
2155 if (err)
2156 goto out_free_candev;
2157
2158 err = mcp251xfd_register(priv);
2159 if (err) {
2160 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2161 mcp251xfd_get_model_str(priv));
2162 goto out_can_rx_offload_del;
2163 }
2164
2165 return 0;
2166
2167 out_can_rx_offload_del:
2168 can_rx_offload_del(&priv->offload);
2169 out_free_candev:
2170 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2171
2172 free_candev(ndev);
2173
2174 return err;
2175 }
2176
mcp251xfd_remove(struct spi_device * spi)2177 static void mcp251xfd_remove(struct spi_device *spi)
2178 {
2179 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2180 struct net_device *ndev = priv->ndev;
2181
2182 can_rx_offload_del(&priv->offload);
2183 mcp251xfd_unregister(priv);
2184 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2185 free_candev(ndev);
2186 }
2187
mcp251xfd_runtime_suspend(struct device * device)2188 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2189 {
2190 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2191
2192 return mcp251xfd_clks_and_vdd_disable(priv);
2193 }
2194
mcp251xfd_runtime_resume(struct device * device)2195 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2196 {
2197 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2198
2199 return mcp251xfd_clks_and_vdd_enable(priv);
2200 }
2201
2202 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2203 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2204 mcp251xfd_runtime_resume, NULL)
2205 };
2206
2207 static struct spi_driver mcp251xfd_driver = {
2208 .driver = {
2209 .name = DEVICE_NAME,
2210 .pm = &mcp251xfd_pm_ops,
2211 .of_match_table = mcp251xfd_of_match,
2212 },
2213 .probe = mcp251xfd_probe,
2214 .remove = mcp251xfd_remove,
2215 .id_table = mcp251xfd_id_table,
2216 };
2217 module_spi_driver(mcp251xfd_driver);
2218
2219 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2220 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2221 MODULE_LICENSE("GPL v2");
2222