1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Microchip Technology
4 */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/mii.h>
8 #include <linux/ethtool.h>
9 #include <linux/phy.h>
10 #include <linux/microchipphy.h>
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <dt-bindings/net/microchip-lan78xx.h>
14
15 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
16 #define DRIVER_DESC "Microchip LAN88XX PHY driver"
17
18 struct lan88xx_priv {
19 int chip_id;
20 int chip_rev;
21 __u32 wolopts;
22 };
23
lan88xx_read_page(struct phy_device * phydev)24 static int lan88xx_read_page(struct phy_device *phydev)
25 {
26 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
27 }
28
lan88xx_write_page(struct phy_device * phydev,int page)29 static int lan88xx_write_page(struct phy_device *phydev, int page)
30 {
31 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
32 }
33
lan88xx_suspend(struct phy_device * phydev)34 static int lan88xx_suspend(struct phy_device *phydev)
35 {
36 struct lan88xx_priv *priv = phydev->priv;
37
38 /* do not power down PHY when WOL is enabled */
39 if (!priv->wolopts)
40 genphy_suspend(phydev);
41
42 return 0;
43 }
44
lan88xx_TR_reg_set(struct phy_device * phydev,u16 regaddr,u32 data)45 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
46 u32 data)
47 {
48 int val, save_page, ret = 0;
49 u16 buf;
50
51 /* Save current page */
52 save_page = phy_save_page(phydev);
53 if (save_page < 0) {
54 phydev_warn(phydev, "Failed to get current page\n");
55 goto err;
56 }
57
58 /* Switch to TR page */
59 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
60
61 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
62 (data & 0xFFFF));
63 if (ret < 0) {
64 phydev_warn(phydev, "Failed to write TR low data\n");
65 goto err;
66 }
67
68 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
69 (data & 0x00FF0000) >> 16);
70 if (ret < 0) {
71 phydev_warn(phydev, "Failed to write TR high data\n");
72 goto err;
73 }
74
75 /* Config control bits [15:13] of register */
76 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
77 buf |= 0x8000; /* Set [15] to Packet transmit */
78
79 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
80 if (ret < 0) {
81 phydev_warn(phydev, "Failed to write data in reg\n");
82 goto err;
83 }
84
85 usleep_range(1000, 2000);/* Wait for Data to be written */
86 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
87 if (!(val & 0x8000))
88 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
89 regaddr);
90 err:
91 return phy_restore_page(phydev, save_page, ret);
92 }
93
lan88xx_config_TR_regs(struct phy_device * phydev)94 static void lan88xx_config_TR_regs(struct phy_device *phydev)
95 {
96 int err;
97
98 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
99 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
100 * MrvlTrFix1000Kp, MasterEnableTR bits.
101 */
102 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
103 if (err < 0)
104 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
105
106 /* Get access to Channel b'10, Node b'1101, Register 0x06.
107 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
108 * SSTrKp1000Mas bits.
109 */
110 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
111 if (err < 0)
112 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
113
114 /* Get access to Channel b'10, Node b'1111, Register 0x11.
115 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
116 * bits
117 */
118 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
119 if (err < 0)
120 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
121
122 /* Get access to Channel b'10, Node b'1101, Register 0x10.
123 * Write 24-bit value 0xEEFFDD to register. Setting
124 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
125 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
126 */
127 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
128 if (err < 0)
129 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
130
131 /* Get access to Channel b'10, Node b'1101, Register 0x13.
132 * Write 24-bit value 0x071448 to register. Setting
133 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
134 */
135 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
136 if (err < 0)
137 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
138
139 /* Get access to Channel b'10, Node b'1101, Register 0x12.
140 * Write 24-bit value 0x13132F to register. Setting
141 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
142 */
143 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
144 if (err < 0)
145 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
146
147 /* Get access to Channel b'10, Node b'1101, Register 0x14.
148 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
149 * eee_TrKf_freeze_delay bits.
150 */
151 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
152 if (err < 0)
153 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
154
155 /* Get access to Channel b'01, Node b'1111, Register 0x34.
156 * Write 24-bit value 0x91B06C to register. Setting
157 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
158 * FastMseSearchUpdGain1000 bits.
159 */
160 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
161 if (err < 0)
162 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
163
164 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
165 * Write 24-bit value 0xC0A028 to register. Setting
166 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
167 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
168 */
169 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
170 if (err < 0)
171 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
172
173 /* Get access to Channel b'01, Node b'1111, Register 0x35.
174 * Write 24-bit value 0x041600 to register. Setting
175 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
176 * FastMsePhChangeDelay1000 bits.
177 */
178 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
179 if (err < 0)
180 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
181
182 /* Get access to Channel b'10, Node b'1101, Register 0x03.
183 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
184 */
185 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
186 if (err < 0)
187 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
188 }
189
lan88xx_probe(struct phy_device * phydev)190 static int lan88xx_probe(struct phy_device *phydev)
191 {
192 struct device *dev = &phydev->mdio.dev;
193 struct lan88xx_priv *priv;
194 u32 led_modes[4];
195 int len;
196
197 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
198 if (!priv)
199 return -ENOMEM;
200
201 priv->wolopts = 0;
202
203 len = of_property_read_variable_u32_array(dev->of_node,
204 "microchip,led-modes",
205 led_modes,
206 0,
207 ARRAY_SIZE(led_modes));
208 if (len >= 0) {
209 u32 reg = 0;
210 int i;
211
212 for (i = 0; i < len; i++) {
213 if (led_modes[i] > 15)
214 return -EINVAL;
215 reg |= led_modes[i] << (i * 4);
216 }
217 for (; i < ARRAY_SIZE(led_modes); i++)
218 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
219 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
220 } else if (len == -EOVERFLOW) {
221 return -EINVAL;
222 }
223
224 /* these values can be used to identify internal PHY */
225 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
226 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
227
228 phydev->priv = priv;
229
230 return 0;
231 }
232
lan88xx_remove(struct phy_device * phydev)233 static void lan88xx_remove(struct phy_device *phydev)
234 {
235 struct device *dev = &phydev->mdio.dev;
236 struct lan88xx_priv *priv = phydev->priv;
237
238 if (priv)
239 devm_kfree(dev, priv);
240 }
241
lan88xx_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)242 static int lan88xx_set_wol(struct phy_device *phydev,
243 struct ethtool_wolinfo *wol)
244 {
245 struct lan88xx_priv *priv = phydev->priv;
246
247 priv->wolopts = wol->wolopts;
248
249 return 0;
250 }
251
lan88xx_set_mdix(struct phy_device * phydev)252 static void lan88xx_set_mdix(struct phy_device *phydev)
253 {
254 int buf;
255 int val;
256
257 switch (phydev->mdix_ctrl) {
258 case ETH_TP_MDI:
259 val = LAN88XX_EXT_MODE_CTRL_MDI_;
260 break;
261 case ETH_TP_MDI_X:
262 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
263 break;
264 case ETH_TP_MDI_AUTO:
265 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
266 break;
267 default:
268 return;
269 }
270
271 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
272 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
273 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
274 buf |= val;
275 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
276 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
277 }
278
lan88xx_config_init(struct phy_device * phydev)279 static int lan88xx_config_init(struct phy_device *phydev)
280 {
281 int val;
282
283 /*Zerodetect delay enable */
284 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
285 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
286 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
287
288 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
289 val);
290
291 /* Config DSP registers */
292 lan88xx_config_TR_regs(phydev);
293
294 return 0;
295 }
296
lan88xx_config_aneg(struct phy_device * phydev)297 static int lan88xx_config_aneg(struct phy_device *phydev)
298 {
299 lan88xx_set_mdix(phydev);
300
301 return genphy_config_aneg(phydev);
302 }
303
lan88xx_link_change_notify(struct phy_device * phydev)304 static void lan88xx_link_change_notify(struct phy_device *phydev)
305 {
306 int temp;
307
308 /* At forced 100 F/H mode, chip may fail to set mode correctly
309 * when cable is switched between long(~50+m) and short one.
310 * As workaround, set to 10 before setting to 100
311 * at forced 100 F/H mode.
312 */
313 if (!phydev->autoneg && phydev->speed == 100) {
314 /* disable phy interrupt */
315 temp = phy_read(phydev, LAN88XX_INT_MASK);
316 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
317 phy_write(phydev, LAN88XX_INT_MASK, temp);
318
319 temp = phy_read(phydev, MII_BMCR);
320 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
321 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
322 temp |= BMCR_SPEED100;
323 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
324
325 /* clear pending interrupt generated while workaround */
326 temp = phy_read(phydev, LAN88XX_INT_STS);
327
328 /* enable phy interrupt back */
329 temp = phy_read(phydev, LAN88XX_INT_MASK);
330 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
331 phy_write(phydev, LAN88XX_INT_MASK, temp);
332 }
333 }
334
335 static struct phy_driver microchip_phy_driver[] = {
336 {
337 .phy_id = 0x0007c132,
338 /* This mask (0xfffffff2) is to differentiate from
339 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
340 * and allows future phy_id revisions.
341 */
342 .phy_id_mask = 0xfffffff2,
343 .name = "Microchip LAN88xx",
344
345 /* PHY_GBIT_FEATURES */
346
347 .probe = lan88xx_probe,
348 .remove = lan88xx_remove,
349
350 .config_init = lan88xx_config_init,
351 .config_aneg = lan88xx_config_aneg,
352 .link_change_notify = lan88xx_link_change_notify,
353
354 /* Interrupt handling is broken, do not define related
355 * functions to force polling.
356 */
357
358 .suspend = lan88xx_suspend,
359 .resume = genphy_resume,
360 .set_wol = lan88xx_set_wol,
361 .read_page = lan88xx_read_page,
362 .write_page = lan88xx_write_page,
363 } };
364
365 module_phy_driver(microchip_phy_driver);
366
367 static struct mdio_device_id __maybe_unused microchip_tbl[] = {
368 { 0x0007c132, 0xfffffff2 },
369 { }
370 };
371
372 MODULE_DEVICE_TABLE(mdio, microchip_tbl);
373
374 MODULE_AUTHOR(DRIVER_AUTHOR);
375 MODULE_DESCRIPTION(DRIVER_DESC);
376 MODULE_LICENSE("GPL");
377