1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Genesys Logic, Inc.
4 *
5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6 *
7 * Version: v0.9.0 (2019-08-08)
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/pci.h>
13 #include <linux/mmc/mmc.h>
14 #include <linux/delay.h>
15 #include <linux/of.h>
16 #include <linux/iopoll.h>
17 #include "sdhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
20 #include "cqhci.h"
21
22 /* Genesys Logic extra registers */
23 #define SDHCI_GLI_9750_WT 0x800
24 #define SDHCI_GLI_9750_WT_EN BIT(0)
25 #define GLI_9750_WT_EN_ON 0x1
26 #define GLI_9750_WT_EN_OFF 0x0
27
28 #define PCI_GLI_9750_PM_CTRL 0xFC
29 #define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
30
31 #define PCI_GLI_9750_CORRERR_MASK 0x214
32 #define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
33
34 #define SDHCI_GLI_9750_CFG2 0x848
35 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
36 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F
37
38 #define SDHCI_GLI_9750_DRIVING 0x860
39 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
40 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
41 #define GLI_9750_DRIVING_1_VALUE 0xFFF
42 #define GLI_9750_DRIVING_2_VALUE 0x3
43 #define SDHCI_GLI_9750_SEL_1 BIT(29)
44 #define SDHCI_GLI_9750_SEL_2 BIT(31)
45 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
46
47 #define SDHCI_GLI_9750_PLL 0x864
48 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
49 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
50 #define SDHCI_GLI_9750_PLL_DIR BIT(15)
51 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
52 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
53 #define GLI_9750_PLL_TX2_INV_VALUE 0x1
54 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
55 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
56 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
57
58 #define SDHCI_GLI_9750_PLLSSC 0x86C
59 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
60
61 #define SDHCI_GLI_9750_SW_CTRL 0x874
62 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
63 #define GLI_9750_SW_CTRL_4_VALUE 0x3
64
65 #define SDHCI_GLI_9750_MISC 0x878
66 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
67 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
68 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
69 #define GLI_9750_MISC_TX1_INV_VALUE 0x0
70 #define GLI_9750_MISC_RX_INV_ON 0x1
71 #define GLI_9750_MISC_RX_INV_OFF 0x0
72 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
73 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
74 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)
75
76 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
77 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
78 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
79 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
80 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
81 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
82 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
83 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
84
85 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
86 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
87 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
88
89 #define SDHCI_GLI_9763E_CTRL_HS400 0x7
90
91 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
92 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
93
94 #define PCIE_GLI_9763E_VHS 0x884
95 #define GLI_9763E_VHS_REV GENMASK(19, 16)
96 #define GLI_9763E_VHS_REV_R 0x0
97 #define GLI_9763E_VHS_REV_M 0x1
98 #define GLI_9763E_VHS_REV_W 0x2
99 #define PCIE_GLI_9763E_MB 0x888
100 #define GLI_9763E_MB_CMDQ_OFF BIT(19)
101 #define GLI_9763E_MB_ERP_ON BIT(7)
102 #define PCIE_GLI_9763E_SCR 0x8E0
103 #define GLI_9763E_SCR_AXI_REQ BIT(9)
104
105 #define PCIE_GLI_9763E_CFG 0x8A0
106 #define GLI_9763E_CFG_LPSN_DIS BIT(12)
107
108 #define PCIE_GLI_9763E_CFG2 0x8A4
109 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
110 #define GLI_9763E_CFG2_L1DLY_MID 0x54
111
112 #define PCIE_GLI_9763E_MMC_CTRL 0x960
113 #define GLI_9763E_HS400_SLOW BIT(3)
114
115 #define PCIE_GLI_9763E_CLKRXDLY 0x934
116 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
117 #define GLI_9763E_HS400_RXDLY_5 0x5
118
119 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
120 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
121 SDHCI_TRNS_BLK_CNT_EN | \
122 SDHCI_TRNS_DMA)
123
124 #define PCI_GLI_9755_WT 0x800
125 #define PCI_GLI_9755_WT_EN BIT(0)
126 #define GLI_9755_WT_EN_ON 0x1
127 #define GLI_9755_WT_EN_OFF 0x0
128
129 #define PCI_GLI_9755_PECONF 0x44
130 #define PCI_GLI_9755_LFCLK GENMASK(14, 12)
131 #define PCI_GLI_9755_DMACLK BIT(29)
132 #define PCI_GLI_9755_INVERT_CD BIT(30)
133 #define PCI_GLI_9755_INVERT_WP BIT(31)
134
135 #define PCI_GLI_9755_CFG2 0x48
136 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
137 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F
138
139 #define PCI_GLI_9755_PLL 0x64
140 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
141 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
142 #define PCI_GLI_9755_PLL_DIR BIT(15)
143 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
144 #define PCI_GLI_9755_PLLSSC_EN BIT(31)
145
146 #define PCI_GLI_9755_PLLSSC 0x68
147 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
148
149 #define PCI_GLI_9755_SerDes 0x70
150 #define PCI_GLI_9755_SCP_DIS BIT(19)
151
152 #define PCI_GLI_9755_MISC 0x78
153 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
154
155 #define PCI_GLI_9755_PM_CTRL 0xFC
156 #define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
157
158 #define PCI_GLI_9755_CORRERR_MASK 0x214
159 #define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
160
161 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
162 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
163
164 #define PCIE_GLI_9767_VHS 0x884
165 #define GLI_9767_VHS_REV GENMASK(19, 16)
166 #define GLI_9767_VHS_REV_R 0x0
167 #define GLI_9767_VHS_REV_M 0x1
168 #define GLI_9767_VHS_REV_W 0x2
169
170 #define PCIE_GLI_9767_COM_MAILBOX 0x888
171 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)
172
173 #define PCIE_GLI_9767_CFG 0x8A0
174 #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
175
176 #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8
177 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)
178 #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)
179
180 #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
181 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
182 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
183 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7
184 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)
185 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3
186
187 #define PCIE_GLI_9767_SCR 0x8E0
188 #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6)
189 #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7)
190 #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9)
191 #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10)
192 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16)
193 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17)
194 #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
195 #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
196
197 #define PCIE_GLI_9767_SDHC_CAP 0x91C
198 #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)
199
200 #define PCIE_GLI_9767_SD_PLL_CTL 0x938
201 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
202 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
203 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)
204 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)
205 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)
206
207 #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C
208 #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)
209
210 #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
211 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
212 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
213
214 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
215 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)
216 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64
217
218 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950
219 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)
220
221 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954
222 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)
223
224 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958
225 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)
226
227 #define GLI_MAX_TUNING_LOOP 40
228
229 /* Genesys Logic chipset */
gl9750_wt_on(struct sdhci_host * host)230 static inline void gl9750_wt_on(struct sdhci_host *host)
231 {
232 u32 wt_value;
233 u32 wt_enable;
234
235 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
236 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
237
238 if (wt_enable == GLI_9750_WT_EN_ON)
239 return;
240
241 wt_value &= ~SDHCI_GLI_9750_WT_EN;
242 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
243
244 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
245 }
246
gl9750_wt_off(struct sdhci_host * host)247 static inline void gl9750_wt_off(struct sdhci_host *host)
248 {
249 u32 wt_value;
250 u32 wt_enable;
251
252 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
253 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
254
255 if (wt_enable == GLI_9750_WT_EN_OFF)
256 return;
257
258 wt_value &= ~SDHCI_GLI_9750_WT_EN;
259 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
260
261 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
262 }
263
gli_set_9750(struct sdhci_host * host)264 static void gli_set_9750(struct sdhci_host *host)
265 {
266 u32 driving_value;
267 u32 pll_value;
268 u32 sw_ctrl_value;
269 u32 misc_value;
270 u32 parameter_value;
271 u32 control_value;
272 u16 ctrl2;
273
274 gl9750_wt_on(host);
275
276 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
277 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
278 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
279 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
280 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
281 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
282
283 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
284 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
285 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
286 GLI_9750_DRIVING_1_VALUE);
287 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
288 GLI_9750_DRIVING_2_VALUE);
289 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
290 driving_value |= SDHCI_GLI_9750_SEL_2;
291 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
292
293 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
294 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
295 GLI_9750_SW_CTRL_4_VALUE);
296 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
297
298 /* reset the tuning flow after reinit and before starting tuning */
299 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
300 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
301 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
302 GLI_9750_PLL_TX2_INV_VALUE);
303 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
304 GLI_9750_PLL_TX2_DLY_VALUE);
305
306 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
307 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
308 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
309 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
310 GLI_9750_MISC_TX1_INV_VALUE);
311 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
312 GLI_9750_MISC_RX_INV_VALUE);
313 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
314 GLI_9750_MISC_TX1_DLY_VALUE);
315
316 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
317 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
318 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
319
320 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
321 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
322 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
323 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
324 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
325 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
326
327 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
328 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
329
330 /* disable tuned clk */
331 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
332 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
333 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
334
335 /* enable tuning parameters control */
336 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
337 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
338 GLI_9750_TUNING_CONTROL_EN_ON);
339 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
340
341 /* write tuning parameters */
342 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
343
344 /* disable tuning parameters control */
345 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
346 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
347 GLI_9750_TUNING_CONTROL_EN_OFF);
348 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
349
350 /* clear tuned clk */
351 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
352 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
353 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
354
355 gl9750_wt_off(host);
356 }
357
gli_set_9750_rx_inv(struct sdhci_host * host,bool b)358 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
359 {
360 u32 misc_value;
361
362 gl9750_wt_on(host);
363
364 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
365 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
366 if (b) {
367 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
368 GLI_9750_MISC_RX_INV_ON);
369 } else {
370 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
371 GLI_9750_MISC_RX_INV_OFF);
372 }
373 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
374
375 gl9750_wt_off(host);
376 }
377
__sdhci_execute_tuning_9750(struct sdhci_host * host,u32 opcode)378 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
379 {
380 int i;
381 int rx_inv;
382
383 for (rx_inv = 0; rx_inv < 2; rx_inv++) {
384 gli_set_9750_rx_inv(host, !!rx_inv);
385 sdhci_start_tuning(host);
386
387 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
388 u16 ctrl;
389
390 sdhci_send_tuning(host, opcode);
391
392 if (!host->tuning_done) {
393 sdhci_abort_tuning(host, opcode);
394 break;
395 }
396
397 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
398 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
399 if (ctrl & SDHCI_CTRL_TUNED_CLK)
400 return 0; /* Success! */
401 break;
402 }
403 }
404 }
405 if (!host->tuning_done) {
406 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
407 mmc_hostname(host->mmc));
408 return -ETIMEDOUT;
409 }
410
411 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
412 mmc_hostname(host->mmc));
413 sdhci_reset_tuning(host);
414
415 return -EAGAIN;
416 }
417
gl9750_execute_tuning(struct sdhci_host * host,u32 opcode)418 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
419 {
420 host->mmc->retune_period = 0;
421 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
422 host->mmc->retune_period = host->tuning_count;
423
424 gli_set_9750(host);
425 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
426 sdhci_end_tuning(host);
427
428 return 0;
429 }
430
gl9750_disable_ssc_pll(struct sdhci_host * host)431 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
432 {
433 u32 pll;
434
435 gl9750_wt_on(host);
436 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
437 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
438 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
439 gl9750_wt_off(host);
440 }
441
gl9750_set_pll(struct sdhci_host * host,u8 dir,u16 ldiv,u8 pdiv)442 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
443 {
444 u32 pll;
445
446 gl9750_wt_on(host);
447 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
448 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
449 SDHCI_GLI_9750_PLL_PDIV |
450 SDHCI_GLI_9750_PLL_DIR);
451 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
452 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
453 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
454 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
455 gl9750_wt_off(host);
456
457 /* wait for pll stable */
458 mdelay(1);
459 }
460
gl9750_ssc_enable(struct sdhci_host * host)461 static bool gl9750_ssc_enable(struct sdhci_host *host)
462 {
463 u32 misc;
464 u8 off;
465
466 gl9750_wt_on(host);
467 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
468 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
469 gl9750_wt_off(host);
470
471 return !off;
472 }
473
gl9750_set_ssc(struct sdhci_host * host,u8 enable,u8 step,u16 ppm)474 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
475 {
476 u32 pll;
477 u32 ssc;
478
479 gl9750_wt_on(host);
480 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
481 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
482 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
483 SDHCI_GLI_9750_PLLSSC_EN);
484 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
485 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
486 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
487 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
488 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
489 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
490 gl9750_wt_off(host);
491 }
492
gl9750_set_ssc_pll_205mhz(struct sdhci_host * host)493 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
494 {
495 bool enable = gl9750_ssc_enable(host);
496
497 /* set pll to 205MHz and ssc */
498 gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
499 gl9750_set_pll(host, 0x1, 0x246, 0x0);
500 }
501
gl9750_set_ssc_pll_100mhz(struct sdhci_host * host)502 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
503 {
504 bool enable = gl9750_ssc_enable(host);
505
506 /* set pll to 100MHz and ssc */
507 gl9750_set_ssc(host, enable, 0xE, 0x51EC);
508 gl9750_set_pll(host, 0x1, 0x244, 0x1);
509 }
510
gl9750_set_ssc_pll_50mhz(struct sdhci_host * host)511 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
512 {
513 bool enable = gl9750_ssc_enable(host);
514
515 /* set pll to 50MHz and ssc */
516 gl9750_set_ssc(host, enable, 0xE, 0x51EC);
517 gl9750_set_pll(host, 0x1, 0x244, 0x3);
518 }
519
sdhci_gl9750_set_clock(struct sdhci_host * host,unsigned int clock)520 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
521 {
522 struct mmc_ios *ios = &host->mmc->ios;
523 u16 clk;
524
525 host->mmc->actual_clock = 0;
526
527 gl9750_disable_ssc_pll(host);
528 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
529
530 if (clock == 0)
531 return;
532
533 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
534 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
535 host->mmc->actual_clock = 205000000;
536 gl9750_set_ssc_pll_205mhz(host);
537 } else if (clock == 100000000) {
538 gl9750_set_ssc_pll_100mhz(host);
539 } else if (clock == 50000000) {
540 gl9750_set_ssc_pll_50mhz(host);
541 }
542
543 sdhci_enable_clk(host, clk);
544 }
545
gl9750_hw_setting(struct sdhci_host * host)546 static void gl9750_hw_setting(struct sdhci_host *host)
547 {
548 struct sdhci_pci_slot *slot = sdhci_priv(host);
549 struct pci_dev *pdev;
550 u32 value;
551
552 pdev = slot->chip->pdev;
553
554 gl9750_wt_on(host);
555
556 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
557 value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
558 /* set ASPM L1 entry delay to 7.9us */
559 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
560 GLI_9750_CFG2_L1DLY_VALUE);
561 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
562
563 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */
564 pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
565 value |= PCI_GLI_9750_PM_STATE;
566 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
567 value &= ~PCI_GLI_9750_PM_STATE;
568 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
569
570 /* mask the replay timer timeout of AER */
571 pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
572 value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
573 pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
574
575 gl9750_wt_off(host);
576 }
577
gli_pcie_enable_msi(struct sdhci_pci_slot * slot)578 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
579 {
580 int ret;
581
582 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
583 PCI_IRQ_MSI | PCI_IRQ_MSIX);
584 if (ret < 0) {
585 pr_warn("%s: enable PCI MSI failed, error=%d\n",
586 mmc_hostname(slot->host->mmc), ret);
587 return;
588 }
589
590 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
591 }
592
gl9755_wt_on(struct pci_dev * pdev)593 static inline void gl9755_wt_on(struct pci_dev *pdev)
594 {
595 u32 wt_value;
596 u32 wt_enable;
597
598 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
599 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
600
601 if (wt_enable == GLI_9755_WT_EN_ON)
602 return;
603
604 wt_value &= ~PCI_GLI_9755_WT_EN;
605 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
606
607 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
608 }
609
gl9755_wt_off(struct pci_dev * pdev)610 static inline void gl9755_wt_off(struct pci_dev *pdev)
611 {
612 u32 wt_value;
613 u32 wt_enable;
614
615 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
616 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
617
618 if (wt_enable == GLI_9755_WT_EN_OFF)
619 return;
620
621 wt_value &= ~PCI_GLI_9755_WT_EN;
622 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
623
624 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
625 }
626
gl9755_disable_ssc_pll(struct pci_dev * pdev)627 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
628 {
629 u32 pll;
630
631 gl9755_wt_on(pdev);
632 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
633 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
634 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
635 gl9755_wt_off(pdev);
636 }
637
gl9755_set_pll(struct pci_dev * pdev,u8 dir,u16 ldiv,u8 pdiv)638 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
639 {
640 u32 pll;
641
642 gl9755_wt_on(pdev);
643 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
644 pll &= ~(PCI_GLI_9755_PLL_LDIV |
645 PCI_GLI_9755_PLL_PDIV |
646 PCI_GLI_9755_PLL_DIR);
647 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
648 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
649 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
650 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
651 gl9755_wt_off(pdev);
652
653 /* wait for pll stable */
654 mdelay(1);
655 }
656
gl9755_ssc_enable(struct pci_dev * pdev)657 static bool gl9755_ssc_enable(struct pci_dev *pdev)
658 {
659 u32 misc;
660 u8 off;
661
662 gl9755_wt_on(pdev);
663 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
664 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
665 gl9755_wt_off(pdev);
666
667 return !off;
668 }
669
gl9755_set_ssc(struct pci_dev * pdev,u8 enable,u8 step,u16 ppm)670 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
671 {
672 u32 pll;
673 u32 ssc;
674
675 gl9755_wt_on(pdev);
676 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
677 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
678 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
679 PCI_GLI_9755_PLLSSC_EN);
680 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
681 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
682 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
683 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
684 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
685 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
686 gl9755_wt_off(pdev);
687 }
688
gl9755_set_ssc_pll_205mhz(struct pci_dev * pdev)689 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
690 {
691 bool enable = gl9755_ssc_enable(pdev);
692
693 /* set pll to 205MHz and ssc */
694 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
695 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
696 }
697
gl9755_set_ssc_pll_100mhz(struct pci_dev * pdev)698 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
699 {
700 bool enable = gl9755_ssc_enable(pdev);
701
702 /* set pll to 100MHz and ssc */
703 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
704 gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
705 }
706
gl9755_set_ssc_pll_50mhz(struct pci_dev * pdev)707 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
708 {
709 bool enable = gl9755_ssc_enable(pdev);
710
711 /* set pll to 50MHz and ssc */
712 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
713 gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
714 }
715
sdhci_gl9755_set_clock(struct sdhci_host * host,unsigned int clock)716 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
717 {
718 struct sdhci_pci_slot *slot = sdhci_priv(host);
719 struct mmc_ios *ios = &host->mmc->ios;
720 struct pci_dev *pdev;
721 u16 clk;
722
723 pdev = slot->chip->pdev;
724 host->mmc->actual_clock = 0;
725
726 gl9755_disable_ssc_pll(pdev);
727 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
728
729 if (clock == 0)
730 return;
731
732 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
733 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
734 host->mmc->actual_clock = 205000000;
735 gl9755_set_ssc_pll_205mhz(pdev);
736 } else if (clock == 100000000) {
737 gl9755_set_ssc_pll_100mhz(pdev);
738 } else if (clock == 50000000) {
739 gl9755_set_ssc_pll_50mhz(pdev);
740 }
741
742 sdhci_enable_clk(host, clk);
743 }
744
gl9755_hw_setting(struct sdhci_pci_slot * slot)745 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
746 {
747 struct pci_dev *pdev = slot->chip->pdev;
748 u32 value;
749
750 gl9755_wt_on(pdev);
751
752 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
753 /*
754 * Apple ARM64 platforms using these chips may have
755 * inverted CD/WP detection.
756 */
757 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
758 value |= PCI_GLI_9755_INVERT_CD;
759 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
760 value |= PCI_GLI_9755_INVERT_WP;
761 value &= ~PCI_GLI_9755_LFCLK;
762 value &= ~PCI_GLI_9755_DMACLK;
763 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
764
765 /* enable short circuit protection */
766 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
767 value &= ~PCI_GLI_9755_SCP_DIS;
768 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
769
770 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
771 value &= ~PCI_GLI_9755_CFG2_L1DLY;
772 /* set ASPM L1 entry delay to 7.9us */
773 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
774 GLI_9755_CFG2_L1DLY_VALUE);
775 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
776
777 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
778 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
779 value |= PCI_GLI_9755_PM_STATE;
780 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
781 value &= ~PCI_GLI_9755_PM_STATE;
782 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
783
784 /* mask the replay timer timeout of AER */
785 pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
786 value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
787 pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
788
789 gl9755_wt_off(pdev);
790 }
791
gl9767_vhs_read(struct pci_dev * pdev)792 static inline void gl9767_vhs_read(struct pci_dev *pdev)
793 {
794 u32 vhs_enable;
795 u32 vhs_value;
796
797 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
798 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
799
800 if (vhs_enable == GLI_9767_VHS_REV_R)
801 return;
802
803 vhs_value &= ~GLI_9767_VHS_REV;
804 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
805
806 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
807 }
808
gl9767_vhs_write(struct pci_dev * pdev)809 static inline void gl9767_vhs_write(struct pci_dev *pdev)
810 {
811 u32 vhs_enable;
812 u32 vhs_value;
813
814 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
815 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
816
817 if (vhs_enable == GLI_9767_VHS_REV_W)
818 return;
819
820 vhs_value &= ~GLI_9767_VHS_REV;
821 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
822
823 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
824 }
825
gl9767_ssc_enable(struct pci_dev * pdev)826 static bool gl9767_ssc_enable(struct pci_dev *pdev)
827 {
828 u32 value;
829 u8 enable;
830
831 gl9767_vhs_write(pdev);
832
833 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
834 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
835
836 gl9767_vhs_read(pdev);
837
838 return enable;
839 }
840
gl9767_set_ssc(struct pci_dev * pdev,u8 enable,u8 step,u16 ppm)841 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
842 {
843 u32 pll;
844 u32 ssc;
845
846 gl9767_vhs_write(pdev);
847
848 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
849 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
850 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
851 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
852 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
853 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
854 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
855 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
856 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
857 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
858
859 gl9767_vhs_read(pdev);
860 }
861
gl9767_set_pll(struct pci_dev * pdev,u8 dir,u16 ldiv,u8 pdiv)862 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
863 {
864 u32 pll;
865
866 gl9767_vhs_write(pdev);
867
868 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
869 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
870 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
871 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
872 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
873 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
874 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
875 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
876
877 gl9767_vhs_read(pdev);
878
879 /* wait for pll stable */
880 usleep_range(1000, 1100);
881 }
882
gl9767_set_ssc_pll_205mhz(struct pci_dev * pdev)883 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
884 {
885 bool enable = gl9767_ssc_enable(pdev);
886
887 /* set pll to 205MHz and ssc */
888 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
889 gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
890 }
891
gl9767_disable_ssc_pll(struct pci_dev * pdev)892 static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
893 {
894 u32 pll;
895
896 gl9767_vhs_write(pdev);
897
898 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
899 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
900 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
901
902 gl9767_vhs_read(pdev);
903 }
904
gl9767_set_low_power_negotiation(struct pci_dev * pdev,bool enable)905 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)
906 {
907 u32 value;
908
909 gl9767_vhs_write(pdev);
910
911 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
912 if (enable)
913 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
914 else
915 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
916 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
917
918 gl9767_vhs_read(pdev);
919 }
920
sdhci_gl9767_set_clock(struct sdhci_host * host,unsigned int clock)921 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
922 {
923 struct sdhci_pci_slot *slot = sdhci_priv(host);
924 struct mmc_ios *ios = &host->mmc->ios;
925 struct pci_dev *pdev;
926 u16 clk;
927
928 pdev = slot->chip->pdev;
929 host->mmc->actual_clock = 0;
930
931 gl9767_set_low_power_negotiation(pdev, false);
932 gl9767_disable_ssc_pll(pdev);
933 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
934
935 if (clock == 0) {
936 gl9767_set_low_power_negotiation(pdev, true);
937 return;
938 }
939
940 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
941 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
942 host->mmc->actual_clock = 205000000;
943 gl9767_set_ssc_pll_205mhz(pdev);
944 }
945
946 sdhci_enable_clk(host, clk);
947 gl9767_set_low_power_negotiation(pdev, true);
948 }
949
gli_set_9767(struct sdhci_host * host)950 static void gli_set_9767(struct sdhci_host *host)
951 {
952 u32 value;
953
954 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
955 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
956 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
957 }
958
gl9767_hw_setting(struct sdhci_pci_slot * slot)959 static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
960 {
961 struct pci_dev *pdev = slot->chip->pdev;
962 u32 value;
963
964 gl9767_vhs_write(pdev);
965
966 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
967 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
968 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
969 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
970
971 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
972 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
973 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
974 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
975 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
976 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
977
978 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
979 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
980 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
981 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
982
983 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
984 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
985 PCIE_GLI_9767_SCR_AXI_REQ |
986 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
987 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
988 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
989
990 gl9767_vhs_read(pdev);
991 }
992
sdhci_gl9767_reset(struct sdhci_host * host,u8 mask)993 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
994 {
995 sdhci_reset(host, mask);
996 gli_set_9767(host);
997 }
998
gl9767_init_sd_express(struct mmc_host * mmc,struct mmc_ios * ios)999 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1000 {
1001 struct sdhci_host *host = mmc_priv(mmc);
1002 struct sdhci_pci_slot *slot = sdhci_priv(host);
1003 struct pci_dev *pdev;
1004 u32 value;
1005 int i;
1006
1007 pdev = slot->chip->pdev;
1008
1009 if (mmc->ops->get_ro(mmc)) {
1010 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
1011 return 0;
1012 }
1013
1014 gl9767_vhs_write(pdev);
1015
1016 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
1017 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
1018 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
1019
1020 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
1021 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
1022 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
1023 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
1024 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1025
1026 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1027 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
1028 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
1029
1030 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
1031 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
1032 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
1033
1034 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
1035 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
1036 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
1037
1038 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1039 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1040 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1041
1042 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1043 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1044 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1045
1046 value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1047 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1048 sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1049
1050 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1051 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
1052 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1053
1054 for (i = 0; i < 2; i++) {
1055 usleep_range(10000, 10100);
1056 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1057 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
1058 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
1059 value);
1060 break;
1061 }
1062 }
1063
1064 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
1065 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
1066 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1067 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
1068 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1069 } else {
1070 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
1071
1072 value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1073 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1074 sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1075
1076 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1077 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1078 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1079 }
1080
1081 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1082 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1083 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1084 gl9767_vhs_read(pdev);
1085
1086 return 0;
1087 }
1088
gli_probe_slot_gl9750(struct sdhci_pci_slot * slot)1089 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
1090 {
1091 struct sdhci_host *host = slot->host;
1092
1093 gl9750_hw_setting(host);
1094 gli_pcie_enable_msi(slot);
1095 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1096 sdhci_enable_v4_mode(host);
1097
1098 return 0;
1099 }
1100
gli_probe_slot_gl9755(struct sdhci_pci_slot * slot)1101 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
1102 {
1103 struct sdhci_host *host = slot->host;
1104
1105 gl9755_hw_setting(slot);
1106 gli_pcie_enable_msi(slot);
1107 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1108 sdhci_enable_v4_mode(host);
1109
1110 return 0;
1111 }
1112
gli_probe_slot_gl9767(struct sdhci_pci_slot * slot)1113 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
1114 {
1115 struct sdhci_host *host = slot->host;
1116
1117 gli_set_9767(host);
1118 gl9767_hw_setting(slot);
1119 gli_pcie_enable_msi(slot);
1120 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1121 host->mmc->caps2 |= MMC_CAP2_SD_EXP;
1122 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
1123 sdhci_enable_v4_mode(host);
1124
1125 return 0;
1126 }
1127
sdhci_gli_voltage_switch(struct sdhci_host * host)1128 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
1129 {
1130 /*
1131 * According to Section 3.6.1 signal voltage switch procedure in
1132 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1133 * follows:
1134 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1135 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1136 * period.
1137 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1138 * step (12).
1139 *
1140 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1141 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
1142 *
1143 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
1144 * slightly longer than 5ms before the control register reports that
1145 * 1.8V is ready, and far longer still before the card will actually
1146 * work reliably.
1147 */
1148 usleep_range(100000, 110000);
1149 }
1150
sdhci_gl9767_voltage_switch(struct sdhci_host * host)1151 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
1152 {
1153 /*
1154 * According to Section 3.6.1 signal voltage switch procedure in
1155 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1156 * follows:
1157 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1158 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1159 * period.
1160 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1161 * step (12).
1162 *
1163 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1164 * to ensure 1.8V signal enable bit is set by GL9767.
1165 *
1166 */
1167 usleep_range(5000, 5500);
1168 }
1169
sdhci_gl9750_reset(struct sdhci_host * host,u8 mask)1170 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
1171 {
1172 sdhci_reset(host, mask);
1173 gli_set_9750(host);
1174 }
1175
sdhci_gl9750_readl(struct sdhci_host * host,int reg)1176 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
1177 {
1178 u32 value;
1179
1180 value = readl(host->ioaddr + reg);
1181 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
1182 value |= 0xc8;
1183
1184 return value;
1185 }
1186
gl9763e_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)1187 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
1188 struct mmc_ios *ios)
1189 {
1190 struct sdhci_host *host = mmc_priv(mmc);
1191 u32 val;
1192
1193 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
1194 if (ios->enhanced_strobe)
1195 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
1196 else
1197 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
1198
1199 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
1200 }
1201
gl9763e_set_low_power_negotiation(struct sdhci_pci_slot * slot,bool enable)1202 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot,
1203 bool enable)
1204 {
1205 struct pci_dev *pdev = slot->chip->pdev;
1206 u32 value;
1207
1208 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1209 value &= ~GLI_9763E_VHS_REV;
1210 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1211 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1212
1213 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
1214
1215 if (enable)
1216 value &= ~GLI_9763E_CFG_LPSN_DIS;
1217 else
1218 value |= GLI_9763E_CFG_LPSN_DIS;
1219
1220 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
1221
1222 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1223 value &= ~GLI_9763E_VHS_REV;
1224 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1225 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1226 }
1227
sdhci_set_gl9763e_signaling(struct sdhci_host * host,unsigned int timing)1228 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
1229 unsigned int timing)
1230 {
1231 u16 ctrl_2;
1232
1233 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1234 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1235 if (timing == MMC_TIMING_MMC_HS200)
1236 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1237 else if (timing == MMC_TIMING_MMC_HS)
1238 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1239 else if (timing == MMC_TIMING_MMC_DDR52)
1240 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1241 else if (timing == MMC_TIMING_MMC_HS400)
1242 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
1243
1244 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1245 }
1246
sdhci_gl9763e_dumpregs(struct mmc_host * mmc)1247 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
1248 {
1249 sdhci_dumpregs(mmc_priv(mmc));
1250 }
1251
sdhci_gl9763e_cqe_pre_enable(struct mmc_host * mmc)1252 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
1253 {
1254 struct cqhci_host *cq_host = mmc->cqe_private;
1255 u32 value;
1256
1257 value = cqhci_readl(cq_host, CQHCI_CFG);
1258 value |= CQHCI_ENABLE;
1259 cqhci_writel(cq_host, value, CQHCI_CFG);
1260 }
1261
sdhci_gl9763e_cqe_enable(struct mmc_host * mmc)1262 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
1263 {
1264 struct sdhci_host *host = mmc_priv(mmc);
1265
1266 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1267 sdhci_cqe_enable(mmc);
1268 }
1269
sdhci_gl9763e_cqhci_irq(struct sdhci_host * host,u32 intmask)1270 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
1271 {
1272 int cmd_error = 0;
1273 int data_error = 0;
1274
1275 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1276 return intmask;
1277
1278 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1279
1280 return 0;
1281 }
1282
sdhci_gl9763e_cqe_post_disable(struct mmc_host * mmc)1283 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
1284 {
1285 struct sdhci_host *host = mmc_priv(mmc);
1286 struct cqhci_host *cq_host = mmc->cqe_private;
1287 u32 value;
1288
1289 value = cqhci_readl(cq_host, CQHCI_CFG);
1290 value &= ~CQHCI_ENABLE;
1291 cqhci_writel(cq_host, value, CQHCI_CFG);
1292 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1293 }
1294
1295 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
1296 .enable = sdhci_gl9763e_cqe_enable,
1297 .disable = sdhci_cqe_disable,
1298 .dumpregs = sdhci_gl9763e_dumpregs,
1299 .pre_enable = sdhci_gl9763e_cqe_pre_enable,
1300 .post_disable = sdhci_gl9763e_cqe_post_disable,
1301 };
1302
gl9763e_add_host(struct sdhci_pci_slot * slot)1303 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
1304 {
1305 struct device *dev = &slot->chip->pdev->dev;
1306 struct sdhci_host *host = slot->host;
1307 struct cqhci_host *cq_host;
1308 bool dma64;
1309 int ret;
1310
1311 ret = sdhci_setup_host(host);
1312 if (ret)
1313 return ret;
1314
1315 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
1316 if (!cq_host) {
1317 ret = -ENOMEM;
1318 goto cleanup;
1319 }
1320
1321 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
1322 cq_host->ops = &sdhci_gl9763e_cqhci_ops;
1323
1324 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1325 if (dma64)
1326 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1327
1328 ret = cqhci_init(cq_host, host->mmc, dma64);
1329 if (ret)
1330 goto cleanup;
1331
1332 ret = __sdhci_add_host(host);
1333 if (ret)
1334 goto cleanup;
1335
1336 /* Disable LPM negotiation to avoid entering L1 state. */
1337 gl9763e_set_low_power_negotiation(slot, false);
1338
1339 return 0;
1340
1341 cleanup:
1342 sdhci_cleanup_host(host);
1343 return ret;
1344 }
1345
gli_set_gl9763e(struct sdhci_pci_slot * slot)1346 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
1347 {
1348 struct pci_dev *pdev = slot->chip->pdev;
1349 u32 value;
1350
1351 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1352 value &= ~GLI_9763E_VHS_REV;
1353 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1354 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1355
1356 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
1357 value |= GLI_9763E_SCR_AXI_REQ;
1358 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
1359
1360 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
1361 value &= ~GLI_9763E_HS400_SLOW;
1362 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
1363
1364 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
1365 value &= ~GLI_9763E_CFG2_L1DLY;
1366 /* set ASPM L1 entry delay to 21us */
1367 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
1368 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
1369
1370 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
1371 value &= ~GLI_9763E_HS400_RXDLY;
1372 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
1373 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1374
1375 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1376 value &= ~GLI_9763E_VHS_REV;
1377 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1378 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1379 }
1380
1381 #ifdef CONFIG_PM
gl9763e_runtime_suspend(struct sdhci_pci_chip * chip)1382 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
1383 {
1384 struct sdhci_pci_slot *slot = chip->slots[0];
1385 struct sdhci_host *host = slot->host;
1386 u16 clock;
1387
1388 /* Enable LPM negotiation to allow entering L1 state */
1389 gl9763e_set_low_power_negotiation(slot, true);
1390
1391 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1392 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
1393 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1394
1395 return 0;
1396 }
1397
gl9763e_runtime_resume(struct sdhci_pci_chip * chip)1398 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
1399 {
1400 struct sdhci_pci_slot *slot = chip->slots[0];
1401 struct sdhci_host *host = slot->host;
1402 u16 clock;
1403
1404 if (host->mmc->ios.power_mode != MMC_POWER_ON)
1405 return 0;
1406
1407 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1408
1409 clock |= SDHCI_CLOCK_PLL_EN;
1410 clock &= ~SDHCI_CLOCK_INT_STABLE;
1411 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1412
1413 /* Wait max 150 ms */
1414 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
1415 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1416 pr_err("%s: PLL clock never stabilised.\n",
1417 mmc_hostname(host->mmc));
1418 sdhci_dumpregs(host);
1419 }
1420
1421 clock |= SDHCI_CLOCK_CARD_EN;
1422 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1423
1424 /* Disable LPM negotiation to avoid entering L1 state. */
1425 gl9763e_set_low_power_negotiation(slot, false);
1426
1427 return 0;
1428 }
1429 #endif
1430
1431 #ifdef CONFIG_PM_SLEEP
sdhci_pci_gli_resume(struct sdhci_pci_chip * chip)1432 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
1433 {
1434 struct sdhci_pci_slot *slot = chip->slots[0];
1435
1436 pci_free_irq_vectors(slot->chip->pdev);
1437 gli_pcie_enable_msi(slot);
1438
1439 return sdhci_pci_resume_host(chip);
1440 }
1441
gl9763e_resume(struct sdhci_pci_chip * chip)1442 static int gl9763e_resume(struct sdhci_pci_chip *chip)
1443 {
1444 struct sdhci_pci_slot *slot = chip->slots[0];
1445 int ret;
1446
1447 ret = sdhci_pci_gli_resume(chip);
1448 if (ret)
1449 return ret;
1450
1451 ret = cqhci_resume(slot->host->mmc);
1452 if (ret)
1453 return ret;
1454
1455 /*
1456 * Disable LPM negotiation to bring device back in sync
1457 * with its runtime_pm state.
1458 */
1459 gl9763e_set_low_power_negotiation(slot, false);
1460
1461 return 0;
1462 }
1463
gl9763e_suspend(struct sdhci_pci_chip * chip)1464 static int gl9763e_suspend(struct sdhci_pci_chip *chip)
1465 {
1466 struct sdhci_pci_slot *slot = chip->slots[0];
1467 int ret;
1468
1469 /*
1470 * Certain SoCs can suspend only with the bus in low-
1471 * power state, notably x86 SoCs when using S0ix.
1472 * Re-enable LPM negotiation to allow entering L1 state
1473 * and entering system suspend.
1474 */
1475 gl9763e_set_low_power_negotiation(slot, true);
1476
1477 ret = cqhci_suspend(slot->host->mmc);
1478 if (ret)
1479 goto err_suspend;
1480
1481 ret = sdhci_suspend_host(slot->host);
1482 if (ret)
1483 goto err_suspend_host;
1484
1485 return 0;
1486
1487 err_suspend_host:
1488 cqhci_resume(slot->host->mmc);
1489 err_suspend:
1490 gl9763e_set_low_power_negotiation(slot, false);
1491 return ret;
1492 }
1493 #endif
1494
gli_probe_slot_gl9763e(struct sdhci_pci_slot * slot)1495 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
1496 {
1497 struct pci_dev *pdev = slot->chip->pdev;
1498 struct sdhci_host *host = slot->host;
1499 u32 value;
1500
1501 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1502 MMC_CAP_1_8V_DDR |
1503 MMC_CAP_NONREMOVABLE;
1504 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1505 MMC_CAP2_HS400_1_8V |
1506 MMC_CAP2_HS400_ES |
1507 MMC_CAP2_NO_SDIO |
1508 MMC_CAP2_NO_SD;
1509
1510 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1511 if (!(value & GLI_9763E_MB_CMDQ_OFF))
1512 if (value & GLI_9763E_MB_ERP_ON)
1513 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1514
1515 gli_pcie_enable_msi(slot);
1516 host->mmc_host_ops.hs400_enhanced_strobe =
1517 gl9763e_hs400_enhanced_strobe;
1518 gli_set_gl9763e(slot);
1519 sdhci_enable_v4_mode(host);
1520
1521 return 0;
1522 }
1523
1524 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1525
sdhci_gli_readw(struct sdhci_host * host,int reg)1526 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1527 {
1528 u32 val = readl(host->ioaddr + (reg & ~3));
1529 u16 word;
1530
1531 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1532 return word;
1533 }
1534
sdhci_gli_readb(struct sdhci_host * host,int reg)1535 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1536 {
1537 u32 val = readl(host->ioaddr + (reg & ~3));
1538 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1539
1540 return byte;
1541 }
1542
1543 static const struct sdhci_ops sdhci_gl9755_ops = {
1544 .read_w = sdhci_gli_readw,
1545 .read_b = sdhci_gli_readb,
1546 .set_clock = sdhci_gl9755_set_clock,
1547 .enable_dma = sdhci_pci_enable_dma,
1548 .set_bus_width = sdhci_set_bus_width,
1549 .reset = sdhci_reset,
1550 .set_uhs_signaling = sdhci_set_uhs_signaling,
1551 .voltage_switch = sdhci_gli_voltage_switch,
1552 };
1553
1554 const struct sdhci_pci_fixes sdhci_gl9755 = {
1555 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1556 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1557 .probe_slot = gli_probe_slot_gl9755,
1558 .ops = &sdhci_gl9755_ops,
1559 #ifdef CONFIG_PM_SLEEP
1560 .resume = sdhci_pci_gli_resume,
1561 #endif
1562 };
1563
1564 static const struct sdhci_ops sdhci_gl9750_ops = {
1565 .read_w = sdhci_gli_readw,
1566 .read_b = sdhci_gli_readb,
1567 .read_l = sdhci_gl9750_readl,
1568 .set_clock = sdhci_gl9750_set_clock,
1569 .enable_dma = sdhci_pci_enable_dma,
1570 .set_bus_width = sdhci_set_bus_width,
1571 .reset = sdhci_gl9750_reset,
1572 .set_uhs_signaling = sdhci_set_uhs_signaling,
1573 .voltage_switch = sdhci_gli_voltage_switch,
1574 .platform_execute_tuning = gl9750_execute_tuning,
1575 };
1576
1577 const struct sdhci_pci_fixes sdhci_gl9750 = {
1578 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1579 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1580 .probe_slot = gli_probe_slot_gl9750,
1581 .ops = &sdhci_gl9750_ops,
1582 #ifdef CONFIG_PM_SLEEP
1583 .resume = sdhci_pci_gli_resume,
1584 #endif
1585 };
1586
1587 static const struct sdhci_ops sdhci_gl9763e_ops = {
1588 .set_clock = sdhci_set_clock,
1589 .enable_dma = sdhci_pci_enable_dma,
1590 .set_bus_width = sdhci_set_bus_width,
1591 .reset = sdhci_and_cqhci_reset,
1592 .set_uhs_signaling = sdhci_set_gl9763e_signaling,
1593 .voltage_switch = sdhci_gli_voltage_switch,
1594 .irq = sdhci_gl9763e_cqhci_irq,
1595 };
1596
1597 const struct sdhci_pci_fixes sdhci_gl9763e = {
1598 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1599 .probe_slot = gli_probe_slot_gl9763e,
1600 .ops = &sdhci_gl9763e_ops,
1601 #ifdef CONFIG_PM_SLEEP
1602 .resume = gl9763e_resume,
1603 .suspend = gl9763e_suspend,
1604 #endif
1605 #ifdef CONFIG_PM
1606 .runtime_suspend = gl9763e_runtime_suspend,
1607 .runtime_resume = gl9763e_runtime_resume,
1608 .allow_runtime_pm = true,
1609 #endif
1610 .add_host = gl9763e_add_host,
1611 };
1612
1613 static const struct sdhci_ops sdhci_gl9767_ops = {
1614 .set_clock = sdhci_gl9767_set_clock,
1615 .enable_dma = sdhci_pci_enable_dma,
1616 .set_bus_width = sdhci_set_bus_width,
1617 .reset = sdhci_gl9767_reset,
1618 .set_uhs_signaling = sdhci_set_uhs_signaling,
1619 .voltage_switch = sdhci_gl9767_voltage_switch,
1620 };
1621
1622 const struct sdhci_pci_fixes sdhci_gl9767 = {
1623 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1624 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1625 .probe_slot = gli_probe_slot_gl9767,
1626 .ops = &sdhci_gl9767_ops,
1627 #ifdef CONFIG_PM_SLEEP
1628 .resume = sdhci_pci_gli_resume,
1629 #endif
1630 };
1631