1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * adv7180.c Analog Devices ADV7180 video decoder driver
4 * Copyright (c) 2009 Intel Corporation
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 */
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/interrupt.h>
13 #include <linux/i2c.h>
14 #include <linux/slab.h>
15 #include <linux/of.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ctrls.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
24
25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
29 #define ADV7180_STD_NTSC_J 0x4
30 #define ADV7180_STD_NTSC_M 0x5
31 #define ADV7180_STD_PAL60 0x6
32 #define ADV7180_STD_NTSC_443 0x7
33 #define ADV7180_STD_PAL_BG 0x8
34 #define ADV7180_STD_PAL_N 0x9
35 #define ADV7180_STD_PAL_M 0xa
36 #define ADV7180_STD_PAL_M_PED 0xb
37 #define ADV7180_STD_PAL_COMB_N 0xc
38 #define ADV7180_STD_PAL_COMB_N_PED 0xd
39 #define ADV7180_STD_PAL_SECAM 0xe
40 #define ADV7180_STD_PAL_SECAM_PED 0xf
41
42 #define ADV7180_REG_INPUT_CONTROL 0x0000
43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
44
45 #define ADV7182_REG_INPUT_VIDSEL 0x0002
46 #define ADV7182_REG_INPUT_RESERVED BIT(2)
47
48 #define ADV7180_REG_OUTPUT_CONTROL 0x0003
49 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
50 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
51
52 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
53 #define ADV7180_AUTODETECT_DEFAULT 0x7f
54 /* Contrast */
55 #define ADV7180_REG_CON 0x0008 /*Unsigned */
56 #define ADV7180_CON_MIN 0
57 #define ADV7180_CON_DEF 128
58 #define ADV7180_CON_MAX 255
59 /* Brightness*/
60 #define ADV7180_REG_BRI 0x000a /*Signed */
61 #define ADV7180_BRI_MIN -128
62 #define ADV7180_BRI_DEF 0
63 #define ADV7180_BRI_MAX 127
64 /* Hue */
65 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
66 #define ADV7180_HUE_MIN -127
67 #define ADV7180_HUE_DEF 0
68 #define ADV7180_HUE_MAX 128
69
70 #define ADV7180_REG_DEF_VALUE_Y 0x000c
71 #define ADV7180_DEF_VAL_EN 0x1
72 #define ADV7180_DEF_VAL_AUTO_EN 0x2
73 #define ADV7180_REG_CTRL 0x000e
74 #define ADV7180_CTRL_IRQ_SPACE 0x20
75
76 #define ADV7180_REG_PWR_MAN 0x0f
77 #define ADV7180_PWR_MAN_ON 0x04
78 #define ADV7180_PWR_MAN_OFF 0x24
79 #define ADV7180_PWR_MAN_RES 0x80
80
81 #define ADV7180_REG_STATUS1 0x0010
82 #define ADV7180_STATUS1_IN_LOCK 0x01
83 #define ADV7180_STATUS1_AUTOD_MASK 0x70
84 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
85 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
86 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
87 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
88 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
89 #define ADV7180_STATUS1_AUTOD_SECAM 0x50
90 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
91 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
92
93 #define ADV7180_REG_IDENT 0x0011
94 #define ADV7180_ID_7180 0x18
95
96 #define ADV7180_REG_STATUS3 0x0013
97 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
98 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
99 #define ADV7180_REG_CTRL_2 0x001d
100 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
101 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
102 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
103 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
104 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
105 #define ADV7180_REG_LOCK_CNT 0x0051
106 #define ADV7180_REG_CVBS_TRIM 0x0052
107 #define ADV7180_REG_CLAMP_ADJ 0x005a
108 #define ADV7180_REG_RES_CIR 0x005f
109 #define ADV7180_REG_DIFF_MODE 0x0060
110
111 #define ADV7180_REG_ICONF1 0x2040
112 #define ADV7180_ICONF1_ACTIVE_LOW 0x01
113 #define ADV7180_ICONF1_PSYNC_ONLY 0x10
114 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
115 /* Saturation */
116 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
117 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
118 #define ADV7180_SAT_MIN 0
119 #define ADV7180_SAT_DEF 128
120 #define ADV7180_SAT_MAX 255
121
122 #define ADV7180_IRQ1_LOCK 0x01
123 #define ADV7180_IRQ1_UNLOCK 0x02
124 #define ADV7180_REG_ISR1 0x2042
125 #define ADV7180_REG_ICR1 0x2043
126 #define ADV7180_REG_IMR1 0x2044
127 #define ADV7180_REG_IMR2 0x2048
128 #define ADV7180_IRQ3_AD_CHANGE 0x08
129 #define ADV7180_REG_ISR3 0x204A
130 #define ADV7180_REG_ICR3 0x204B
131 #define ADV7180_REG_IMR3 0x204C
132 #define ADV7180_REG_IMR4 0x2050
133
134 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
135 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
136
137 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
138 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
139
140 #define ADV7180_REG_ACE_CTRL1 0x4080
141 #define ADV7180_REG_ACE_CTRL5 0x4084
142 #define ADV7180_REG_FLCONTROL 0x40e0
143 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
144
145 #define ADV7180_REG_RST_CLAMP 0x809c
146 #define ADV7180_REG_AGC_ADJ1 0x80b6
147 #define ADV7180_REG_AGC_ADJ2 0x80c0
148
149 #define ADV7180_CSI_REG_PWRDN 0x00
150 #define ADV7180_CSI_PWRDN 0x80
151
152 #define ADV7180_INPUT_CVBS_AIN1 0x00
153 #define ADV7180_INPUT_CVBS_AIN2 0x01
154 #define ADV7180_INPUT_CVBS_AIN3 0x02
155 #define ADV7180_INPUT_CVBS_AIN4 0x03
156 #define ADV7180_INPUT_CVBS_AIN5 0x04
157 #define ADV7180_INPUT_CVBS_AIN6 0x05
158 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
159 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
160 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
161 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
162 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
163
164 #define ADV7182_INPUT_CVBS_AIN1 0x00
165 #define ADV7182_INPUT_CVBS_AIN2 0x01
166 #define ADV7182_INPUT_CVBS_AIN3 0x02
167 #define ADV7182_INPUT_CVBS_AIN4 0x03
168 #define ADV7182_INPUT_CVBS_AIN5 0x04
169 #define ADV7182_INPUT_CVBS_AIN6 0x05
170 #define ADV7182_INPUT_CVBS_AIN7 0x06
171 #define ADV7182_INPUT_CVBS_AIN8 0x07
172 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
173 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
174 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
175 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
176 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
177 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
178 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
179 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
180 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
181 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
182
183 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
184 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
185
186 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
187
188 /* Initial number of frames to skip to avoid possible garbage */
189 #define ADV7180_NUM_OF_SKIP_FRAMES 2
190
191 struct adv7180_state;
192
193 #define ADV7180_FLAG_RESET_POWERED BIT(0)
194 #define ADV7180_FLAG_V2 BIT(1)
195 #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
196 #define ADV7180_FLAG_I2P BIT(3)
197 #define ADV7180_FLAG_TEST_PATTERN BIT(4)
198
199 struct adv7180_chip_info {
200 unsigned int flags;
201 unsigned int valid_input_mask;
202 int (*set_std)(struct adv7180_state *st, unsigned int std);
203 int (*select_input)(struct adv7180_state *st, unsigned int input);
204 int (*init)(struct adv7180_state *state);
205 };
206
207 struct adv7180_state {
208 struct v4l2_ctrl_handler ctrl_hdl;
209 struct v4l2_subdev sd;
210 struct media_pad pad;
211 struct mutex mutex; /* mutual excl. when accessing chip */
212 int irq;
213 struct gpio_desc *pwdn_gpio;
214 struct gpio_desc *rst_gpio;
215 v4l2_std_id curr_norm;
216 bool powered;
217 bool streaming;
218 u8 input;
219
220 struct i2c_client *client;
221 unsigned int register_page;
222 struct i2c_client *csi_client;
223 struct i2c_client *vpp_client;
224 const struct adv7180_chip_info *chip_info;
225 enum v4l2_field field;
226 bool force_bt656_4;
227 };
228 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
229 struct adv7180_state, \
230 ctrl_hdl)->sd)
231
adv7180_select_page(struct adv7180_state * state,unsigned int page)232 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
233 {
234 if (state->register_page != page) {
235 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
236 page);
237 state->register_page = page;
238 }
239
240 return 0;
241 }
242
adv7180_write(struct adv7180_state * state,unsigned int reg,unsigned int value)243 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
244 unsigned int value)
245 {
246 lockdep_assert_held(&state->mutex);
247 adv7180_select_page(state, reg >> 8);
248 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
249 }
250
adv7180_read(struct adv7180_state * state,unsigned int reg)251 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
252 {
253 lockdep_assert_held(&state->mutex);
254 adv7180_select_page(state, reg >> 8);
255 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
256 }
257
adv7180_csi_write(struct adv7180_state * state,unsigned int reg,unsigned int value)258 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
259 unsigned int value)
260 {
261 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
262 }
263
adv7180_set_video_standard(struct adv7180_state * state,unsigned int std)264 static int adv7180_set_video_standard(struct adv7180_state *state,
265 unsigned int std)
266 {
267 return state->chip_info->set_std(state, std);
268 }
269
adv7180_vpp_write(struct adv7180_state * state,unsigned int reg,unsigned int value)270 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
271 unsigned int value)
272 {
273 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
274 }
275
adv7180_std_to_v4l2(u8 status1)276 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
277 {
278 /* in case V4L2_IN_ST_NO_SIGNAL */
279 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
280 return V4L2_STD_UNKNOWN;
281
282 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
283 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
284 return V4L2_STD_NTSC;
285 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
286 return V4L2_STD_NTSC_443;
287 case ADV7180_STATUS1_AUTOD_PAL_M:
288 return V4L2_STD_PAL_M;
289 case ADV7180_STATUS1_AUTOD_PAL_60:
290 return V4L2_STD_PAL_60;
291 case ADV7180_STATUS1_AUTOD_PAL_B_G:
292 return V4L2_STD_PAL;
293 case ADV7180_STATUS1_AUTOD_SECAM:
294 return V4L2_STD_SECAM;
295 case ADV7180_STATUS1_AUTOD_PAL_COMB:
296 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
297 case ADV7180_STATUS1_AUTOD_SECAM_525:
298 return V4L2_STD_SECAM;
299 default:
300 return V4L2_STD_UNKNOWN;
301 }
302 }
303
v4l2_std_to_adv7180(v4l2_std_id std)304 static int v4l2_std_to_adv7180(v4l2_std_id std)
305 {
306 if (std == V4L2_STD_PAL_60)
307 return ADV7180_STD_PAL60;
308 if (std == V4L2_STD_NTSC_443)
309 return ADV7180_STD_NTSC_443;
310 if (std == V4L2_STD_PAL_N)
311 return ADV7180_STD_PAL_N;
312 if (std == V4L2_STD_PAL_M)
313 return ADV7180_STD_PAL_M;
314 if (std == V4L2_STD_PAL_Nc)
315 return ADV7180_STD_PAL_COMB_N;
316
317 if (std & V4L2_STD_PAL)
318 return ADV7180_STD_PAL_BG;
319 if (std & V4L2_STD_NTSC)
320 return ADV7180_STD_NTSC_M;
321 if (std & V4L2_STD_SECAM)
322 return ADV7180_STD_PAL_SECAM;
323
324 return -EINVAL;
325 }
326
adv7180_status_to_v4l2(u8 status1)327 static u32 adv7180_status_to_v4l2(u8 status1)
328 {
329 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
330 return V4L2_IN_ST_NO_SIGNAL;
331
332 return 0;
333 }
334
__adv7180_status(struct adv7180_state * state,u32 * status,v4l2_std_id * std)335 static int __adv7180_status(struct adv7180_state *state, u32 *status,
336 v4l2_std_id *std)
337 {
338 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
339
340 if (status1 < 0)
341 return status1;
342
343 if (status)
344 *status = adv7180_status_to_v4l2(status1);
345 if (std)
346 *std = adv7180_std_to_v4l2(status1);
347
348 return 0;
349 }
350
to_state(struct v4l2_subdev * sd)351 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
352 {
353 return container_of(sd, struct adv7180_state, sd);
354 }
355
adv7180_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)356 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
357 {
358 struct adv7180_state *state = to_state(sd);
359 int err = mutex_lock_interruptible(&state->mutex);
360 if (err)
361 return err;
362
363 if (state->streaming) {
364 err = -EBUSY;
365 goto unlock;
366 }
367
368 err = adv7180_set_video_standard(state,
369 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
370 if (err)
371 goto unlock;
372
373 msleep(100);
374 __adv7180_status(state, NULL, std);
375
376 err = v4l2_std_to_adv7180(state->curr_norm);
377 if (err < 0)
378 goto unlock;
379
380 err = adv7180_set_video_standard(state, err);
381
382 unlock:
383 mutex_unlock(&state->mutex);
384 return err;
385 }
386
adv7180_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)387 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
388 u32 output, u32 config)
389 {
390 struct adv7180_state *state = to_state(sd);
391 int ret = mutex_lock_interruptible(&state->mutex);
392
393 if (ret)
394 return ret;
395
396 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
397 ret = -EINVAL;
398 goto out;
399 }
400
401 ret = state->chip_info->select_input(state, input);
402
403 if (ret == 0)
404 state->input = input;
405 out:
406 mutex_unlock(&state->mutex);
407 return ret;
408 }
409
adv7180_g_input_status(struct v4l2_subdev * sd,u32 * status)410 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
411 {
412 struct adv7180_state *state = to_state(sd);
413 int ret = mutex_lock_interruptible(&state->mutex);
414 if (ret)
415 return ret;
416
417 ret = __adv7180_status(state, status, NULL);
418 mutex_unlock(&state->mutex);
419 return ret;
420 }
421
adv7180_program_std(struct adv7180_state * state)422 static int adv7180_program_std(struct adv7180_state *state)
423 {
424 int ret;
425
426 ret = v4l2_std_to_adv7180(state->curr_norm);
427 if (ret < 0)
428 return ret;
429
430 ret = adv7180_set_video_standard(state, ret);
431 if (ret < 0)
432 return ret;
433 return 0;
434 }
435
adv7180_s_std(struct v4l2_subdev * sd,v4l2_std_id std)436 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
437 {
438 struct adv7180_state *state = to_state(sd);
439 int ret = mutex_lock_interruptible(&state->mutex);
440
441 if (ret)
442 return ret;
443
444 /* Make sure we can support this std */
445 ret = v4l2_std_to_adv7180(std);
446 if (ret < 0)
447 goto out;
448
449 state->curr_norm = std;
450
451 ret = adv7180_program_std(state);
452 out:
453 mutex_unlock(&state->mutex);
454 return ret;
455 }
456
adv7180_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)457 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
458 {
459 struct adv7180_state *state = to_state(sd);
460
461 *norm = state->curr_norm;
462
463 return 0;
464 }
465
adv7180_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)466 static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
467 struct v4l2_subdev_frame_interval *fi)
468 {
469 struct adv7180_state *state = to_state(sd);
470
471 if (state->curr_norm & V4L2_STD_525_60) {
472 fi->interval.numerator = 1001;
473 fi->interval.denominator = 30000;
474 } else {
475 fi->interval.numerator = 1;
476 fi->interval.denominator = 25;
477 }
478
479 return 0;
480 }
481
adv7180_set_power_pin(struct adv7180_state * state,bool on)482 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
483 {
484 if (!state->pwdn_gpio)
485 return;
486
487 if (on) {
488 gpiod_set_value_cansleep(state->pwdn_gpio, 0);
489 usleep_range(5000, 10000);
490 } else {
491 gpiod_set_value_cansleep(state->pwdn_gpio, 1);
492 }
493 }
494
adv7180_set_reset_pin(struct adv7180_state * state,bool on)495 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
496 {
497 if (!state->rst_gpio)
498 return;
499
500 if (on) {
501 gpiod_set_value_cansleep(state->rst_gpio, 1);
502 } else {
503 gpiod_set_value_cansleep(state->rst_gpio, 0);
504 usleep_range(5000, 10000);
505 }
506 }
507
adv7180_set_power(struct adv7180_state * state,bool on)508 static int adv7180_set_power(struct adv7180_state *state, bool on)
509 {
510 u8 val;
511 int ret;
512
513 if (on)
514 val = ADV7180_PWR_MAN_ON;
515 else
516 val = ADV7180_PWR_MAN_OFF;
517
518 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
519 if (ret)
520 return ret;
521
522 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
523 if (on) {
524 adv7180_csi_write(state, 0xDE, 0x02);
525 adv7180_csi_write(state, 0xD2, 0xF7);
526 adv7180_csi_write(state, 0xD8, 0x65);
527 adv7180_csi_write(state, 0xE0, 0x09);
528 adv7180_csi_write(state, 0x2C, 0x00);
529 if (state->field == V4L2_FIELD_NONE)
530 adv7180_csi_write(state, 0x1D, 0x80);
531 adv7180_csi_write(state, 0x00, 0x00);
532 } else {
533 adv7180_csi_write(state, 0x00, 0x80);
534 }
535 }
536
537 return 0;
538 }
539
adv7180_s_power(struct v4l2_subdev * sd,int on)540 static int adv7180_s_power(struct v4l2_subdev *sd, int on)
541 {
542 struct adv7180_state *state = to_state(sd);
543 int ret;
544
545 ret = mutex_lock_interruptible(&state->mutex);
546 if (ret)
547 return ret;
548
549 ret = adv7180_set_power(state, on);
550 if (ret == 0)
551 state->powered = on;
552
553 mutex_unlock(&state->mutex);
554 return ret;
555 }
556
557 static const char * const test_pattern_menu[] = {
558 "Single color",
559 "Color bars",
560 "Luma ramp",
561 "Boundary box",
562 "Disable",
563 };
564
adv7180_test_pattern(struct adv7180_state * state,int value)565 static int adv7180_test_pattern(struct adv7180_state *state, int value)
566 {
567 unsigned int reg = 0;
568
569 /* Map menu value into register value */
570 if (value < 3)
571 reg = value;
572 if (value == 3)
573 reg = 5;
574
575 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
576
577 if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
578 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
579 reg &= ~ADV7180_DEF_VAL_EN;
580 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
581 return 0;
582 }
583
584 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
585 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
586 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
587
588 return 0;
589 }
590
adv7180_s_ctrl(struct v4l2_ctrl * ctrl)591 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
592 {
593 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
594 struct adv7180_state *state = to_state(sd);
595 int ret = mutex_lock_interruptible(&state->mutex);
596 int val;
597
598 if (ret)
599 return ret;
600 val = ctrl->val;
601 switch (ctrl->id) {
602 case V4L2_CID_BRIGHTNESS:
603 ret = adv7180_write(state, ADV7180_REG_BRI, val);
604 break;
605 case V4L2_CID_HUE:
606 /*Hue is inverted according to HSL chart */
607 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
608 break;
609 case V4L2_CID_CONTRAST:
610 ret = adv7180_write(state, ADV7180_REG_CON, val);
611 break;
612 case V4L2_CID_SATURATION:
613 /*
614 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
615 *Let's not confuse the user, everybody understands saturation
616 */
617 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
618 if (ret < 0)
619 break;
620 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
621 break;
622 case V4L2_CID_ADV_FAST_SWITCH:
623 if (ctrl->val) {
624 /* ADI required write */
625 adv7180_write(state, 0x80d9, 0x44);
626 adv7180_write(state, ADV7180_REG_FLCONTROL,
627 ADV7180_FLCONTROL_FL_ENABLE);
628 } else {
629 /* ADI required write */
630 adv7180_write(state, 0x80d9, 0xc4);
631 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
632 }
633 break;
634 case V4L2_CID_TEST_PATTERN:
635 ret = adv7180_test_pattern(state, val);
636 break;
637 default:
638 ret = -EINVAL;
639 }
640
641 mutex_unlock(&state->mutex);
642 return ret;
643 }
644
645 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
646 .s_ctrl = adv7180_s_ctrl,
647 };
648
649 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
650 .ops = &adv7180_ctrl_ops,
651 .id = V4L2_CID_ADV_FAST_SWITCH,
652 .name = "Fast Switching",
653 .type = V4L2_CTRL_TYPE_BOOLEAN,
654 .min = 0,
655 .max = 1,
656 .step = 1,
657 };
658
adv7180_init_controls(struct adv7180_state * state)659 static int adv7180_init_controls(struct adv7180_state *state)
660 {
661 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
662
663 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
664 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
665 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
666 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
667 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
668 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
669 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
670 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
671 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
672 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
673 V4L2_CID_HUE, ADV7180_HUE_MIN,
674 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
675 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
676
677 if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) {
678 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl,
679 &adv7180_ctrl_ops,
680 V4L2_CID_TEST_PATTERN,
681 ARRAY_SIZE(test_pattern_menu) - 1,
682 0,
683 ARRAY_SIZE(test_pattern_menu) - 1,
684 test_pattern_menu);
685 }
686
687 state->sd.ctrl_handler = &state->ctrl_hdl;
688 if (state->ctrl_hdl.error) {
689 int err = state->ctrl_hdl.error;
690
691 v4l2_ctrl_handler_free(&state->ctrl_hdl);
692 return err;
693 }
694 v4l2_ctrl_handler_setup(&state->ctrl_hdl);
695
696 return 0;
697 }
adv7180_exit_controls(struct adv7180_state * state)698 static void adv7180_exit_controls(struct adv7180_state *state)
699 {
700 v4l2_ctrl_handler_free(&state->ctrl_hdl);
701 }
702
adv7180_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)703 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
704 struct v4l2_subdev_state *sd_state,
705 struct v4l2_subdev_mbus_code_enum *code)
706 {
707 if (code->index != 0)
708 return -EINVAL;
709
710 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
711
712 return 0;
713 }
714
adv7180_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)715 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
716 struct v4l2_mbus_framefmt *fmt)
717 {
718 struct adv7180_state *state = to_state(sd);
719
720 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
721 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
722 fmt->width = 720;
723 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
724
725 if (state->field == V4L2_FIELD_ALTERNATE)
726 fmt->height /= 2;
727
728 return 0;
729 }
730
adv7180_set_field_mode(struct adv7180_state * state)731 static int adv7180_set_field_mode(struct adv7180_state *state)
732 {
733 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
734 return 0;
735
736 if (state->field == V4L2_FIELD_NONE) {
737 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
738 adv7180_csi_write(state, 0x01, 0x20);
739 adv7180_csi_write(state, 0x02, 0x28);
740 adv7180_csi_write(state, 0x03, 0x38);
741 adv7180_csi_write(state, 0x04, 0x30);
742 adv7180_csi_write(state, 0x05, 0x30);
743 adv7180_csi_write(state, 0x06, 0x80);
744 adv7180_csi_write(state, 0x07, 0x70);
745 adv7180_csi_write(state, 0x08, 0x50);
746 }
747 adv7180_vpp_write(state, 0xa3, 0x00);
748 adv7180_vpp_write(state, 0x5b, 0x00);
749 adv7180_vpp_write(state, 0x55, 0x80);
750 } else {
751 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
752 adv7180_csi_write(state, 0x01, 0x18);
753 adv7180_csi_write(state, 0x02, 0x18);
754 adv7180_csi_write(state, 0x03, 0x30);
755 adv7180_csi_write(state, 0x04, 0x20);
756 adv7180_csi_write(state, 0x05, 0x28);
757 adv7180_csi_write(state, 0x06, 0x40);
758 adv7180_csi_write(state, 0x07, 0x58);
759 adv7180_csi_write(state, 0x08, 0x30);
760 }
761 adv7180_vpp_write(state, 0xa3, 0x70);
762 adv7180_vpp_write(state, 0x5b, 0x80);
763 adv7180_vpp_write(state, 0x55, 0x00);
764 }
765
766 return 0;
767 }
768
adv7180_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)769 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
770 struct v4l2_subdev_state *sd_state,
771 struct v4l2_subdev_format *format)
772 {
773 struct adv7180_state *state = to_state(sd);
774
775 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
776 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
777 } else {
778 adv7180_mbus_fmt(sd, &format->format);
779 format->format.field = state->field;
780 }
781
782 return 0;
783 }
784
adv7180_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)785 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
786 struct v4l2_subdev_state *sd_state,
787 struct v4l2_subdev_format *format)
788 {
789 struct adv7180_state *state = to_state(sd);
790 struct v4l2_mbus_framefmt *framefmt;
791 int ret;
792
793 switch (format->format.field) {
794 case V4L2_FIELD_NONE:
795 if (state->chip_info->flags & ADV7180_FLAG_I2P)
796 break;
797 fallthrough;
798 default:
799 format->format.field = V4L2_FIELD_ALTERNATE;
800 break;
801 }
802
803 ret = adv7180_mbus_fmt(sd, &format->format);
804
805 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
806 if (state->field != format->format.field) {
807 state->field = format->format.field;
808 adv7180_set_power(state, false);
809 adv7180_set_field_mode(state);
810 adv7180_set_power(state, true);
811 }
812 } else {
813 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
814 *framefmt = format->format;
815 }
816
817 return ret;
818 }
819
adv7180_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)820 static int adv7180_init_cfg(struct v4l2_subdev *sd,
821 struct v4l2_subdev_state *sd_state)
822 {
823 struct v4l2_subdev_format fmt = {
824 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
825 : V4L2_SUBDEV_FORMAT_ACTIVE,
826 };
827
828 return adv7180_set_pad_format(sd, sd_state, &fmt);
829 }
830
adv7180_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)831 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
832 unsigned int pad,
833 struct v4l2_mbus_config *cfg)
834 {
835 struct adv7180_state *state = to_state(sd);
836
837 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
838 cfg->type = V4L2_MBUS_CSI2_DPHY;
839 cfg->bus.mipi_csi2.num_data_lanes = 1;
840 cfg->bus.mipi_csi2.flags = 0;
841 } else {
842 /*
843 * The ADV7180 sensor supports BT.601/656 output modes.
844 * The BT.656 is default and not yet configurable by s/w.
845 */
846 cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
847 V4L2_MBUS_PCLK_SAMPLE_RISING |
848 V4L2_MBUS_DATA_ACTIVE_HIGH;
849 cfg->type = V4L2_MBUS_BT656;
850 }
851
852 return 0;
853 }
854
adv7180_get_skip_frames(struct v4l2_subdev * sd,u32 * frames)855 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
856 {
857 *frames = ADV7180_NUM_OF_SKIP_FRAMES;
858
859 return 0;
860 }
861
adv7180_g_pixelaspect(struct v4l2_subdev * sd,struct v4l2_fract * aspect)862 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
863 {
864 struct adv7180_state *state = to_state(sd);
865
866 if (state->curr_norm & V4L2_STD_525_60) {
867 aspect->numerator = 11;
868 aspect->denominator = 10;
869 } else {
870 aspect->numerator = 54;
871 aspect->denominator = 59;
872 }
873
874 return 0;
875 }
876
adv7180_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)877 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
878 {
879 *norm = V4L2_STD_ALL;
880 return 0;
881 }
882
adv7180_s_stream(struct v4l2_subdev * sd,int enable)883 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
884 {
885 struct adv7180_state *state = to_state(sd);
886 int ret;
887
888 /* It's always safe to stop streaming, no need to take the lock */
889 if (!enable) {
890 state->streaming = enable;
891 return 0;
892 }
893
894 /* Must wait until querystd released the lock */
895 ret = mutex_lock_interruptible(&state->mutex);
896 if (ret)
897 return ret;
898 state->streaming = enable;
899 mutex_unlock(&state->mutex);
900 return 0;
901 }
902
adv7180_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)903 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
904 struct v4l2_fh *fh,
905 struct v4l2_event_subscription *sub)
906 {
907 switch (sub->type) {
908 case V4L2_EVENT_SOURCE_CHANGE:
909 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
910 case V4L2_EVENT_CTRL:
911 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
912 default:
913 return -EINVAL;
914 }
915 }
916
917 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
918 .s_std = adv7180_s_std,
919 .g_std = adv7180_g_std,
920 .g_frame_interval = adv7180_g_frame_interval,
921 .querystd = adv7180_querystd,
922 .g_input_status = adv7180_g_input_status,
923 .s_routing = adv7180_s_routing,
924 .g_pixelaspect = adv7180_g_pixelaspect,
925 .g_tvnorms = adv7180_g_tvnorms,
926 .s_stream = adv7180_s_stream,
927 };
928
929 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
930 .s_power = adv7180_s_power,
931 .subscribe_event = adv7180_subscribe_event,
932 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
933 };
934
935 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
936 .init_cfg = adv7180_init_cfg,
937 .enum_mbus_code = adv7180_enum_mbus_code,
938 .set_fmt = adv7180_set_pad_format,
939 .get_fmt = adv7180_get_pad_format,
940 .get_mbus_config = adv7180_get_mbus_config,
941 };
942
943 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
944 .g_skip_frames = adv7180_get_skip_frames,
945 };
946
947 static const struct v4l2_subdev_ops adv7180_ops = {
948 .core = &adv7180_core_ops,
949 .video = &adv7180_video_ops,
950 .pad = &adv7180_pad_ops,
951 .sensor = &adv7180_sensor_ops,
952 };
953
adv7180_irq(int irq,void * devid)954 static irqreturn_t adv7180_irq(int irq, void *devid)
955 {
956 struct adv7180_state *state = devid;
957 u8 isr3;
958
959 mutex_lock(&state->mutex);
960 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
961 /* clear */
962 adv7180_write(state, ADV7180_REG_ICR3, isr3);
963
964 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
965 static const struct v4l2_event src_ch = {
966 .type = V4L2_EVENT_SOURCE_CHANGE,
967 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
968 };
969
970 v4l2_subdev_notify_event(&state->sd, &src_ch);
971 }
972 mutex_unlock(&state->mutex);
973
974 return IRQ_HANDLED;
975 }
976
adv7180_init(struct adv7180_state * state)977 static int adv7180_init(struct adv7180_state *state)
978 {
979 int ret;
980
981 /* ITU-R BT.656-4 compatible */
982 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
983 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
984 if (ret < 0)
985 return ret;
986
987 /* Manually set V bit end position in NTSC mode */
988 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
989 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
990 }
991
adv7180_set_std(struct adv7180_state * state,unsigned int std)992 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
993 {
994 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
995 (std << 4) | state->input);
996 }
997
adv7180_select_input(struct adv7180_state * state,unsigned int input)998 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
999 {
1000 int ret;
1001
1002 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
1003 if (ret < 0)
1004 return ret;
1005
1006 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1007 ret |= input;
1008 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1009 }
1010
adv7182_init(struct adv7180_state * state)1011 static int adv7182_init(struct adv7180_state *state)
1012 {
1013 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1014 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1015 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
1016
1017 if (state->chip_info->flags & ADV7180_FLAG_I2P)
1018 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1019 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
1020
1021 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1022 /* ADI recommended writes for improved video quality */
1023 adv7180_write(state, 0x0080, 0x51);
1024 adv7180_write(state, 0x0081, 0x51);
1025 adv7180_write(state, 0x0082, 0x68);
1026 }
1027
1028 /* ADI required writes */
1029 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1030 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1031 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1032 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1033 } else {
1034 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1035 if (state->force_bt656_4) {
1036 /* ITU-R BT.656-4 compatible */
1037 adv7180_write(state,
1038 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1039 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1040 /* Manually set NEWAVMODE */
1041 adv7180_write(state,
1042 ADV7180_REG_VSYNC_FIELD_CTL_1,
1043 ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1044 /* Manually set V bit end position in NTSC mode */
1045 adv7180_write(state,
1046 ADV7180_REG_NTSC_V_BIT_END,
1047 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1048 } else {
1049 adv7180_write(state,
1050 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1051 0x17);
1052 }
1053 }
1054 else
1055 adv7180_write(state,
1056 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1057 0x07);
1058 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1059 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1060 }
1061
1062 adv7180_write(state, 0x0013, 0x00);
1063
1064 return 0;
1065 }
1066
adv7182_set_std(struct adv7180_state * state,unsigned int std)1067 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1068 {
1069 /* Failing to set the reserved bit can result in increased video noise */
1070 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1071 (std << 4) | ADV7182_REG_INPUT_RESERVED);
1072 }
1073
1074 enum adv7182_input_type {
1075 ADV7182_INPUT_TYPE_CVBS,
1076 ADV7182_INPUT_TYPE_DIFF_CVBS,
1077 ADV7182_INPUT_TYPE_SVIDEO,
1078 ADV7182_INPUT_TYPE_YPBPR,
1079 };
1080
adv7182_get_input_type(unsigned int input)1081 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1082 {
1083 switch (input) {
1084 case ADV7182_INPUT_CVBS_AIN1:
1085 case ADV7182_INPUT_CVBS_AIN2:
1086 case ADV7182_INPUT_CVBS_AIN3:
1087 case ADV7182_INPUT_CVBS_AIN4:
1088 case ADV7182_INPUT_CVBS_AIN5:
1089 case ADV7182_INPUT_CVBS_AIN6:
1090 case ADV7182_INPUT_CVBS_AIN7:
1091 case ADV7182_INPUT_CVBS_AIN8:
1092 return ADV7182_INPUT_TYPE_CVBS;
1093 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1094 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1095 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1096 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1097 return ADV7182_INPUT_TYPE_SVIDEO;
1098 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1099 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1100 return ADV7182_INPUT_TYPE_YPBPR;
1101 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1102 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1103 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1104 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1105 return ADV7182_INPUT_TYPE_DIFF_CVBS;
1106 default: /* Will never happen */
1107 return 0;
1108 }
1109 }
1110
1111 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1112 static unsigned int adv7182_lbias_settings[][3] = {
1113 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1114 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1115 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1116 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1117 };
1118
1119 static unsigned int adv7280_lbias_settings[][3] = {
1120 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1121 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1122 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1123 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1124 };
1125
adv7182_select_input(struct adv7180_state * state,unsigned int input)1126 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1127 {
1128 enum adv7182_input_type input_type;
1129 unsigned int *lbias;
1130 unsigned int i;
1131 int ret;
1132
1133 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1134 if (ret)
1135 return ret;
1136
1137 /* Reset clamp circuitry - ADI recommended writes */
1138 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1139 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1140
1141 input_type = adv7182_get_input_type(input);
1142
1143 switch (input_type) {
1144 case ADV7182_INPUT_TYPE_CVBS:
1145 case ADV7182_INPUT_TYPE_DIFF_CVBS:
1146 /* ADI recommends to use the SH1 filter */
1147 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1148 break;
1149 default:
1150 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1151 break;
1152 }
1153
1154 if (state->chip_info->flags & ADV7180_FLAG_V2)
1155 lbias = adv7280_lbias_settings[input_type];
1156 else
1157 lbias = adv7182_lbias_settings[input_type];
1158
1159 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1160 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1161
1162 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1163 /* ADI required writes to make differential CVBS work */
1164 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1165 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1166 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1167 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1168 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1169 } else {
1170 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1171 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1172 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1173 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1174 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1175 }
1176
1177 return 0;
1178 }
1179
1180 static const struct adv7180_chip_info adv7180_info = {
1181 .flags = ADV7180_FLAG_RESET_POWERED,
1182 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1183 * all inputs and let the card driver take care of validation
1184 */
1185 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1186 BIT(ADV7180_INPUT_CVBS_AIN2) |
1187 BIT(ADV7180_INPUT_CVBS_AIN3) |
1188 BIT(ADV7180_INPUT_CVBS_AIN4) |
1189 BIT(ADV7180_INPUT_CVBS_AIN5) |
1190 BIT(ADV7180_INPUT_CVBS_AIN6) |
1191 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1192 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1193 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1194 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1195 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1196 .init = adv7180_init,
1197 .set_std = adv7180_set_std,
1198 .select_input = adv7180_select_input,
1199 };
1200
1201 static const struct adv7180_chip_info adv7182_info = {
1202 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1203 BIT(ADV7182_INPUT_CVBS_AIN2) |
1204 BIT(ADV7182_INPUT_CVBS_AIN3) |
1205 BIT(ADV7182_INPUT_CVBS_AIN4) |
1206 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1207 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1208 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1209 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1210 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1211 .init = adv7182_init,
1212 .set_std = adv7182_set_std,
1213 .select_input = adv7182_select_input,
1214 };
1215
1216 static const struct adv7180_chip_info adv7280_info = {
1217 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1218 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1219 BIT(ADV7182_INPUT_CVBS_AIN2) |
1220 BIT(ADV7182_INPUT_CVBS_AIN3) |
1221 BIT(ADV7182_INPUT_CVBS_AIN4) |
1222 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1223 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1224 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1225 .init = adv7182_init,
1226 .set_std = adv7182_set_std,
1227 .select_input = adv7182_select_input,
1228 };
1229
1230 static const struct adv7180_chip_info adv7280_m_info = {
1231 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1232 ADV7180_FLAG_TEST_PATTERN,
1233 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1234 BIT(ADV7182_INPUT_CVBS_AIN2) |
1235 BIT(ADV7182_INPUT_CVBS_AIN3) |
1236 BIT(ADV7182_INPUT_CVBS_AIN4) |
1237 BIT(ADV7182_INPUT_CVBS_AIN5) |
1238 BIT(ADV7182_INPUT_CVBS_AIN6) |
1239 BIT(ADV7182_INPUT_CVBS_AIN7) |
1240 BIT(ADV7182_INPUT_CVBS_AIN8) |
1241 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1242 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1243 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1244 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1245 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1246 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1247 .init = adv7182_init,
1248 .set_std = adv7182_set_std,
1249 .select_input = adv7182_select_input,
1250 };
1251
1252 static const struct adv7180_chip_info adv7281_info = {
1253 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1254 ADV7180_FLAG_TEST_PATTERN,
1255 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1256 BIT(ADV7182_INPUT_CVBS_AIN2) |
1257 BIT(ADV7182_INPUT_CVBS_AIN7) |
1258 BIT(ADV7182_INPUT_CVBS_AIN8) |
1259 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1260 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1261 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1262 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1263 .init = adv7182_init,
1264 .set_std = adv7182_set_std,
1265 .select_input = adv7182_select_input,
1266 };
1267
1268 static const struct adv7180_chip_info adv7281_m_info = {
1269 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1270 ADV7180_FLAG_TEST_PATTERN,
1271 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1272 BIT(ADV7182_INPUT_CVBS_AIN2) |
1273 BIT(ADV7182_INPUT_CVBS_AIN3) |
1274 BIT(ADV7182_INPUT_CVBS_AIN4) |
1275 BIT(ADV7182_INPUT_CVBS_AIN7) |
1276 BIT(ADV7182_INPUT_CVBS_AIN8) |
1277 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1278 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1279 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1280 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1281 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1282 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1283 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1284 .init = adv7182_init,
1285 .set_std = adv7182_set_std,
1286 .select_input = adv7182_select_input,
1287 };
1288
1289 static const struct adv7180_chip_info adv7281_ma_info = {
1290 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1291 ADV7180_FLAG_TEST_PATTERN,
1292 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1293 BIT(ADV7182_INPUT_CVBS_AIN2) |
1294 BIT(ADV7182_INPUT_CVBS_AIN3) |
1295 BIT(ADV7182_INPUT_CVBS_AIN4) |
1296 BIT(ADV7182_INPUT_CVBS_AIN5) |
1297 BIT(ADV7182_INPUT_CVBS_AIN6) |
1298 BIT(ADV7182_INPUT_CVBS_AIN7) |
1299 BIT(ADV7182_INPUT_CVBS_AIN8) |
1300 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1301 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1302 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1303 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1304 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1305 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1306 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1307 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1308 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1309 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1310 .init = adv7182_init,
1311 .set_std = adv7182_set_std,
1312 .select_input = adv7182_select_input,
1313 };
1314
1315 static const struct adv7180_chip_info adv7282_info = {
1316 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1317 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1318 BIT(ADV7182_INPUT_CVBS_AIN2) |
1319 BIT(ADV7182_INPUT_CVBS_AIN7) |
1320 BIT(ADV7182_INPUT_CVBS_AIN8) |
1321 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1322 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1323 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1324 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1325 .init = adv7182_init,
1326 .set_std = adv7182_set_std,
1327 .select_input = adv7182_select_input,
1328 };
1329
1330 static const struct adv7180_chip_info adv7282_m_info = {
1331 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1332 ADV7180_FLAG_TEST_PATTERN,
1333 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1334 BIT(ADV7182_INPUT_CVBS_AIN2) |
1335 BIT(ADV7182_INPUT_CVBS_AIN3) |
1336 BIT(ADV7182_INPUT_CVBS_AIN4) |
1337 BIT(ADV7182_INPUT_CVBS_AIN7) |
1338 BIT(ADV7182_INPUT_CVBS_AIN8) |
1339 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1340 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1341 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1342 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1343 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1344 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1345 .init = adv7182_init,
1346 .set_std = adv7182_set_std,
1347 .select_input = adv7182_select_input,
1348 };
1349
init_device(struct adv7180_state * state)1350 static int init_device(struct adv7180_state *state)
1351 {
1352 int ret;
1353
1354 mutex_lock(&state->mutex);
1355
1356 adv7180_set_power_pin(state, true);
1357 adv7180_set_reset_pin(state, false);
1358
1359 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1360 usleep_range(5000, 10000);
1361
1362 ret = state->chip_info->init(state);
1363 if (ret)
1364 goto out_unlock;
1365
1366 ret = adv7180_program_std(state);
1367 if (ret)
1368 goto out_unlock;
1369
1370 adv7180_set_field_mode(state);
1371
1372 /* register for interrupts */
1373 if (state->irq > 0) {
1374 /* config the Interrupt pin to be active low */
1375 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1376 ADV7180_ICONF1_ACTIVE_LOW |
1377 ADV7180_ICONF1_PSYNC_ONLY);
1378 if (ret < 0)
1379 goto out_unlock;
1380
1381 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1382 if (ret < 0)
1383 goto out_unlock;
1384
1385 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1386 if (ret < 0)
1387 goto out_unlock;
1388
1389 /* enable AD change interrupts interrupts */
1390 ret = adv7180_write(state, ADV7180_REG_IMR3,
1391 ADV7180_IRQ3_AD_CHANGE);
1392 if (ret < 0)
1393 goto out_unlock;
1394
1395 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1396 if (ret < 0)
1397 goto out_unlock;
1398 }
1399
1400 out_unlock:
1401 mutex_unlock(&state->mutex);
1402
1403 return ret;
1404 }
1405
adv7180_probe(struct i2c_client * client)1406 static int adv7180_probe(struct i2c_client *client)
1407 {
1408 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1409 struct device_node *np = client->dev.of_node;
1410 struct adv7180_state *state;
1411 struct v4l2_subdev *sd;
1412 int ret;
1413
1414 /* Check if the adapter supports the needed features */
1415 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1416 return -EIO;
1417
1418 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1419 if (state == NULL)
1420 return -ENOMEM;
1421
1422 state->client = client;
1423 state->field = V4L2_FIELD_ALTERNATE;
1424 state->chip_info = (struct adv7180_chip_info *)id->driver_data;
1425
1426 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1427 GPIOD_OUT_HIGH);
1428 if (IS_ERR(state->pwdn_gpio)) {
1429 ret = PTR_ERR(state->pwdn_gpio);
1430 v4l_err(client, "request for power pin failed: %d\n", ret);
1431 return ret;
1432 }
1433
1434 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1435 GPIOD_OUT_HIGH);
1436 if (IS_ERR(state->rst_gpio)) {
1437 ret = PTR_ERR(state->rst_gpio);
1438 v4l_err(client, "request for reset pin failed: %d\n", ret);
1439 return ret;
1440 }
1441
1442 if (of_property_read_bool(np, "adv,force-bt656-4"))
1443 state->force_bt656_4 = true;
1444
1445 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1446 state->csi_client = i2c_new_dummy_device(client->adapter,
1447 ADV7180_DEFAULT_CSI_I2C_ADDR);
1448 if (IS_ERR(state->csi_client))
1449 return PTR_ERR(state->csi_client);
1450 }
1451
1452 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1453 state->vpp_client = i2c_new_dummy_device(client->adapter,
1454 ADV7180_DEFAULT_VPP_I2C_ADDR);
1455 if (IS_ERR(state->vpp_client)) {
1456 ret = PTR_ERR(state->vpp_client);
1457 goto err_unregister_csi_client;
1458 }
1459 }
1460
1461 state->irq = client->irq;
1462 mutex_init(&state->mutex);
1463 state->curr_norm = V4L2_STD_NTSC;
1464 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1465 state->powered = true;
1466 else
1467 state->powered = false;
1468 state->input = 0;
1469 sd = &state->sd;
1470 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1471 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1472
1473 ret = adv7180_init_controls(state);
1474 if (ret)
1475 goto err_unregister_vpp_client;
1476
1477 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1478 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1479 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1480 if (ret)
1481 goto err_free_ctrl;
1482
1483 ret = init_device(state);
1484 if (ret)
1485 goto err_media_entity_cleanup;
1486
1487 if (state->irq) {
1488 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1489 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1490 KBUILD_MODNAME, state);
1491 if (ret)
1492 goto err_media_entity_cleanup;
1493 }
1494
1495 ret = v4l2_async_register_subdev(sd);
1496 if (ret)
1497 goto err_free_irq;
1498
1499 mutex_lock(&state->mutex);
1500 ret = adv7180_read(state, ADV7180_REG_IDENT);
1501 mutex_unlock(&state->mutex);
1502 if (ret < 0)
1503 goto err_v4l2_async_unregister;
1504
1505 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1506 ret, client->addr, client->adapter->name);
1507
1508 return 0;
1509
1510 err_v4l2_async_unregister:
1511 v4l2_async_unregister_subdev(sd);
1512 err_free_irq:
1513 if (state->irq > 0)
1514 free_irq(client->irq, state);
1515 err_media_entity_cleanup:
1516 media_entity_cleanup(&sd->entity);
1517 err_free_ctrl:
1518 adv7180_exit_controls(state);
1519 err_unregister_vpp_client:
1520 i2c_unregister_device(state->vpp_client);
1521 err_unregister_csi_client:
1522 i2c_unregister_device(state->csi_client);
1523 mutex_destroy(&state->mutex);
1524 return ret;
1525 }
1526
adv7180_remove(struct i2c_client * client)1527 static void adv7180_remove(struct i2c_client *client)
1528 {
1529 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1530 struct adv7180_state *state = to_state(sd);
1531
1532 v4l2_async_unregister_subdev(sd);
1533
1534 if (state->irq > 0)
1535 free_irq(client->irq, state);
1536
1537 media_entity_cleanup(&sd->entity);
1538 adv7180_exit_controls(state);
1539
1540 i2c_unregister_device(state->vpp_client);
1541 i2c_unregister_device(state->csi_client);
1542
1543 adv7180_set_reset_pin(state, true);
1544 adv7180_set_power_pin(state, false);
1545
1546 mutex_destroy(&state->mutex);
1547 }
1548
1549 static const struct i2c_device_id adv7180_id[] = {
1550 { "adv7180", (kernel_ulong_t)&adv7180_info },
1551 { "adv7180cp", (kernel_ulong_t)&adv7180_info },
1552 { "adv7180st", (kernel_ulong_t)&adv7180_info },
1553 { "adv7182", (kernel_ulong_t)&adv7182_info },
1554 { "adv7280", (kernel_ulong_t)&adv7280_info },
1555 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1556 { "adv7281", (kernel_ulong_t)&adv7281_info },
1557 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1558 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1559 { "adv7282", (kernel_ulong_t)&adv7282_info },
1560 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1561 {},
1562 };
1563 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1564
1565 #ifdef CONFIG_PM_SLEEP
adv7180_suspend(struct device * dev)1566 static int adv7180_suspend(struct device *dev)
1567 {
1568 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1569 struct adv7180_state *state = to_state(sd);
1570
1571 return adv7180_set_power(state, false);
1572 }
1573
adv7180_resume(struct device * dev)1574 static int adv7180_resume(struct device *dev)
1575 {
1576 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1577 struct adv7180_state *state = to_state(sd);
1578 int ret;
1579
1580 ret = init_device(state);
1581 if (ret < 0)
1582 return ret;
1583
1584 ret = adv7180_set_power(state, state->powered);
1585 if (ret)
1586 return ret;
1587
1588 return 0;
1589 }
1590
1591 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1592 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1593
1594 #else
1595 #define ADV7180_PM_OPS NULL
1596 #endif
1597
1598 #ifdef CONFIG_OF
1599 static const struct of_device_id adv7180_of_id[] = {
1600 { .compatible = "adi,adv7180", },
1601 { .compatible = "adi,adv7180cp", },
1602 { .compatible = "adi,adv7180st", },
1603 { .compatible = "adi,adv7182", },
1604 { .compatible = "adi,adv7280", },
1605 { .compatible = "adi,adv7280-m", },
1606 { .compatible = "adi,adv7281", },
1607 { .compatible = "adi,adv7281-m", },
1608 { .compatible = "adi,adv7281-ma", },
1609 { .compatible = "adi,adv7282", },
1610 { .compatible = "adi,adv7282-m", },
1611 { },
1612 };
1613
1614 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1615 #endif
1616
1617 static struct i2c_driver adv7180_driver = {
1618 .driver = {
1619 .name = KBUILD_MODNAME,
1620 .pm = ADV7180_PM_OPS,
1621 .of_match_table = of_match_ptr(adv7180_of_id),
1622 },
1623 .probe = adv7180_probe,
1624 .remove = adv7180_remove,
1625 .id_table = adv7180_id,
1626 };
1627
1628 module_i2c_driver(adv7180_driver);
1629
1630 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1631 MODULE_AUTHOR("Mocean Laboratories");
1632 MODULE_LICENSE("GPL v2");
1633