1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_probe_helper.h>
19
20 #include "msm_drv.h"
21 #include "dpu_kms.h"
22 #include "dpu_hwio.h"
23 #include "dpu_hw_catalog.h"
24 #include "dpu_hw_intf.h"
25 #include "dpu_hw_ctl.h"
26 #include "dpu_hw_dspp.h"
27 #include "dpu_hw_dsc.h"
28 #include "dpu_hw_merge3d.h"
29 #include "dpu_formats.h"
30 #include "dpu_encoder_phys.h"
31 #include "dpu_crtc.h"
32 #include "dpu_trace.h"
33 #include "dpu_core_irq.h"
34 #include "disp/msm_disp_snapshot.h"
35
36 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
37 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
38
39 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
40 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
41
42 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
43 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
44
45 /*
46 * Two to anticipate panels that can do cmd/vid dynamic switching
47 * plan is to create all possible physical encoder types, and switch between
48 * them at runtime
49 */
50 #define NUM_PHYS_ENCODER_TYPES 2
51
52 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
53 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
54
55 #define MAX_CHANNELS_PER_ENC 2
56
57 #define IDLE_SHORT_TIMEOUT 1
58
59 #define MAX_HDISPLAY_SPLIT 1080
60
61 /* timeout in frames waiting for frame done */
62 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
63
64 /**
65 * enum dpu_enc_rc_events - events for resource control state machine
66 * @DPU_ENC_RC_EVENT_KICKOFF:
67 * This event happens at NORMAL priority.
68 * Event that signals the start of the transfer. When this event is
69 * received, enable MDP/DSI core clocks. Regardless of the previous
70 * state, the resource should be in ON state at the end of this event.
71 * @DPU_ENC_RC_EVENT_FRAME_DONE:
72 * This event happens at INTERRUPT level.
73 * Event signals the end of the data transfer after the PP FRAME_DONE
74 * event. At the end of this event, a delayed work is scheduled to go to
75 * IDLE_PC state after IDLE_TIMEOUT time.
76 * @DPU_ENC_RC_EVENT_PRE_STOP:
77 * This event happens at NORMAL priority.
78 * This event, when received during the ON state, leave the RC STATE
79 * in the PRE_OFF state. It should be followed by the STOP event as
80 * part of encoder disable.
81 * If received during IDLE or OFF states, it will do nothing.
82 * @DPU_ENC_RC_EVENT_STOP:
83 * This event happens at NORMAL priority.
84 * When this event is received, disable all the MDP/DSI core clocks, and
85 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
86 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
87 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
88 * Resource state should be in OFF at the end of the event.
89 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
90 * This event happens at NORMAL priority from a work item.
91 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
92 * This would disable MDP/DSI core clocks and change the resource state
93 * to IDLE.
94 */
95 enum dpu_enc_rc_events {
96 DPU_ENC_RC_EVENT_KICKOFF = 1,
97 DPU_ENC_RC_EVENT_FRAME_DONE,
98 DPU_ENC_RC_EVENT_PRE_STOP,
99 DPU_ENC_RC_EVENT_STOP,
100 DPU_ENC_RC_EVENT_ENTER_IDLE
101 };
102
103 /*
104 * enum dpu_enc_rc_states - states that the resource control maintains
105 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
106 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
107 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
108 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
109 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
110 */
111 enum dpu_enc_rc_states {
112 DPU_ENC_RC_STATE_OFF,
113 DPU_ENC_RC_STATE_PRE_OFF,
114 DPU_ENC_RC_STATE_ON,
115 DPU_ENC_RC_STATE_IDLE
116 };
117
118 /**
119 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
120 * encoders. Virtual encoder manages one "logical" display. Physical
121 * encoders manage one intf block, tied to a specific panel/sub-panel.
122 * Virtual encoder defers as much as possible to the physical encoders.
123 * Virtual encoder registers itself with the DRM Framework as the encoder.
124 * @base: drm_encoder base class for registration with DRM
125 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
126 * @enabled: True if the encoder is active, protected by enc_lock
127 * @commit_done_timedout: True if there has been a timeout on commit after
128 * enabling the encoder.
129 * @num_phys_encs: Actual number of physical encoders contained.
130 * @phys_encs: Container of physical encoders managed.
131 * @cur_master: Pointer to the current master in this mode. Optimization
132 * Only valid after enable. Cleared as disable.
133 * @cur_slave: As above but for the slave encoder.
134 * @hw_pp: Handle to the pingpong blocks used for the display. No.
135 * pingpong blocks can be different than num_phys_encs.
136 * @hw_dsc: Handle to the DSC blocks used for the display.
137 * @dsc_mask: Bitmask of used DSC blocks.
138 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
139 * for partial update right-only cases, such as pingpong
140 * split where virtual pingpong does not generate IRQs
141 * @crtc: Pointer to the currently assigned crtc. Normally you
142 * would use crtc->state->encoder_mask to determine the
143 * link between encoder/crtc. However in this case we need
144 * to track crtc in the disable() hook which is called
145 * _after_ encoder_mask is cleared.
146 * @connector: If a mode is set, cached pointer to the active connector
147 * @crtc_kickoff_cb: Callback into CRTC that will flush & start
148 * all CTL paths
149 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
150 * @debugfs_root: Debug file system root file node
151 * @enc_lock: Lock around physical encoder
152 * create/destroy/enable/disable
153 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
154 * busy processing current command.
155 * Bit0 = phys_encs[0] etc.
156 * @crtc_frame_event_cb: callback handler for frame event
157 * @crtc_frame_event_cb_data: callback handler private data
158 * @frame_done_timeout_ms: frame done timeout in ms
159 * @frame_done_timer: watchdog timer for frame done event
160 * @disp_info: local copy of msm_display_info struct
161 * @idle_pc_supported: indicate if idle power collaps is supported
162 * @rc_lock: resource control mutex lock to protect
163 * virt encoder over various state changes
164 * @rc_state: resource controller state
165 * @delayed_off_work: delayed worker to schedule disabling of
166 * clks and resources after IDLE_TIMEOUT time.
167 * @topology: topology of the display
168 * @idle_timeout: idle timeout duration in milliseconds
169 * @wide_bus_en: wide bus is enabled on this interface
170 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
171 */
172 struct dpu_encoder_virt {
173 struct drm_encoder base;
174 spinlock_t enc_spinlock;
175
176 bool enabled;
177 bool commit_done_timedout;
178
179 unsigned int num_phys_encs;
180 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
181 struct dpu_encoder_phys *cur_master;
182 struct dpu_encoder_phys *cur_slave;
183 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
184 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
185
186 unsigned int dsc_mask;
187
188 bool intfs_swapped;
189
190 struct drm_crtc *crtc;
191 struct drm_connector *connector;
192
193 struct dentry *debugfs_root;
194 struct mutex enc_lock;
195 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
196 void (*crtc_frame_event_cb)(void *, u32 event);
197 void *crtc_frame_event_cb_data;
198
199 atomic_t frame_done_timeout_ms;
200 struct timer_list frame_done_timer;
201
202 struct msm_display_info disp_info;
203
204 bool idle_pc_supported;
205 struct mutex rc_lock;
206 enum dpu_enc_rc_states rc_state;
207 struct delayed_work delayed_off_work;
208 struct msm_display_topology topology;
209
210 u32 idle_timeout;
211
212 bool wide_bus_en;
213
214 /* DSC configuration */
215 struct drm_dsc_config *dsc;
216 };
217
218 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
219
220 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
221 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
222 };
223
224
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)225 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
226 {
227 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
228
229 return dpu_enc->wide_bus_en;
230 }
231
dpu_encoder_is_dsc_enabled(const struct drm_encoder * drm_enc)232 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
233 {
234 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
235
236 return dpu_enc->dsc ? true : false;
237 }
238
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)239 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
240 {
241 struct dpu_encoder_virt *dpu_enc;
242 int i, num_intf = 0;
243
244 dpu_enc = to_dpu_encoder_virt(drm_enc);
245
246 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
247 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
248
249 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
250 && phys->hw_intf->ops.collect_misr)
251 num_intf++;
252 }
253
254 return num_intf;
255 }
256
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)257 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
258 {
259 struct dpu_encoder_virt *dpu_enc;
260
261 int i;
262
263 dpu_enc = to_dpu_encoder_virt(drm_enc);
264
265 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
266 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
267
268 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
269 continue;
270
271 phys->hw_intf->ops.setup_misr(phys->hw_intf);
272 }
273 }
274
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)275 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
276 {
277 struct dpu_encoder_virt *dpu_enc;
278
279 int i, rc = 0, entries_added = 0;
280
281 if (!drm_enc->crtc) {
282 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
283 return -EINVAL;
284 }
285
286 dpu_enc = to_dpu_encoder_virt(drm_enc);
287
288 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
289 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
290
291 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
292 continue;
293
294 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
295 if (rc)
296 return rc;
297 entries_added++;
298 }
299
300 return entries_added;
301 }
302
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)303 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
304 {
305 struct dpu_hw_dither_cfg dither_cfg = { 0 };
306
307 if (!hw_pp->ops.setup_dither)
308 return;
309
310 switch (bpc) {
311 case 6:
312 dither_cfg.c0_bitdepth = 6;
313 dither_cfg.c1_bitdepth = 6;
314 dither_cfg.c2_bitdepth = 6;
315 dither_cfg.c3_bitdepth = 6;
316 dither_cfg.temporal_en = 0;
317 break;
318 default:
319 hw_pp->ops.setup_dither(hw_pp, NULL);
320 return;
321 }
322
323 memcpy(&dither_cfg.matrix, dither_matrix,
324 sizeof(u32) * DITHER_MATRIX_SZ);
325
326 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
327 }
328
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)329 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
330 {
331 switch (intf_mode) {
332 case INTF_MODE_VIDEO:
333 return "INTF_MODE_VIDEO";
334 case INTF_MODE_CMD:
335 return "INTF_MODE_CMD";
336 case INTF_MODE_WB_BLOCK:
337 return "INTF_MODE_WB_BLOCK";
338 case INTF_MODE_WB_LINE:
339 return "INTF_MODE_WB_LINE";
340 default:
341 return "INTF_MODE_UNKNOWN";
342 }
343 }
344
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)345 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
346 enum dpu_intr_idx intr_idx)
347 {
348 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
349 DRMID(phys_enc->parent),
350 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
351 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
352 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
353 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
354
355 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
356 DPU_ENCODER_FRAME_EVENT_ERROR);
357 }
358
359 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
360 u32 irq_idx, struct dpu_encoder_wait_info *info);
361
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,int irq_idx,void (* func)(void * arg),struct dpu_encoder_wait_info * wait_info)362 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
363 int irq_idx,
364 void (*func)(void *arg),
365 struct dpu_encoder_wait_info *wait_info)
366 {
367 u32 irq_status;
368 int ret;
369
370 if (!wait_info) {
371 DPU_ERROR("invalid params\n");
372 return -EINVAL;
373 }
374 /* note: do master / slave checking outside */
375
376 /* return EWOULDBLOCK since we know the wait isn't necessary */
377 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
378 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
379 DRMID(phys_enc->parent), func,
380 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
381 return -EWOULDBLOCK;
382 }
383
384 if (irq_idx < 0) {
385 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
386 DRMID(phys_enc->parent), func);
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
391 DRMID(phys_enc->parent), func,
392 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
393 atomic_read(wait_info->atomic_cnt));
394
395 ret = dpu_encoder_helper_wait_event_timeout(
396 DRMID(phys_enc->parent),
397 irq_idx,
398 wait_info);
399
400 if (ret <= 0) {
401 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
402 if (irq_status) {
403 unsigned long flags;
404
405 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
406 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
407 DRMID(phys_enc->parent), func,
408 phys_enc->hw_pp->idx - PINGPONG_0,
409 atomic_read(wait_info->atomic_cnt));
410 local_irq_save(flags);
411 func(phys_enc);
412 local_irq_restore(flags);
413 ret = 0;
414 } else {
415 ret = -ETIMEDOUT;
416 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
417 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
418 DRMID(phys_enc->parent), func,
419 phys_enc->hw_pp->idx - PINGPONG_0,
420 atomic_read(wait_info->atomic_cnt));
421 }
422 } else {
423 ret = 0;
424 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
425 func, irq_idx,
426 phys_enc->hw_pp->idx - PINGPONG_0,
427 atomic_read(wait_info->atomic_cnt));
428 }
429
430 return ret;
431 }
432
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)433 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
434 {
435 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
436 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
437 return phys ? atomic_read(&phys->vsync_cnt) : 0;
438 }
439
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)440 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
441 {
442 struct dpu_encoder_virt *dpu_enc;
443 struct dpu_encoder_phys *phys;
444 int linecount = 0;
445
446 dpu_enc = to_dpu_encoder_virt(drm_enc);
447 phys = dpu_enc ? dpu_enc->cur_master : NULL;
448
449 if (phys && phys->ops.get_line_count)
450 linecount = phys->ops.get_line_count(phys);
451
452 return linecount;
453 }
454
dpu_encoder_destroy(struct drm_encoder * drm_enc)455 static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
456 {
457 struct dpu_encoder_virt *dpu_enc = NULL;
458 int i = 0;
459
460 if (!drm_enc) {
461 DPU_ERROR("invalid encoder\n");
462 return;
463 }
464
465 dpu_enc = to_dpu_encoder_virt(drm_enc);
466 DPU_DEBUG_ENC(dpu_enc, "\n");
467
468 mutex_lock(&dpu_enc->enc_lock);
469
470 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
471 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
472
473 if (phys->ops.destroy) {
474 phys->ops.destroy(phys);
475 --dpu_enc->num_phys_encs;
476 dpu_enc->phys_encs[i] = NULL;
477 }
478 }
479
480 if (dpu_enc->num_phys_encs)
481 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
482 dpu_enc->num_phys_encs);
483 dpu_enc->num_phys_encs = 0;
484 mutex_unlock(&dpu_enc->enc_lock);
485
486 drm_encoder_cleanup(drm_enc);
487 mutex_destroy(&dpu_enc->enc_lock);
488 }
489
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)490 void dpu_encoder_helper_split_config(
491 struct dpu_encoder_phys *phys_enc,
492 enum dpu_intf interface)
493 {
494 struct dpu_encoder_virt *dpu_enc;
495 struct split_pipe_cfg cfg = { 0 };
496 struct dpu_hw_mdp *hw_mdptop;
497 struct msm_display_info *disp_info;
498
499 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
500 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
501 return;
502 }
503
504 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
505 hw_mdptop = phys_enc->hw_mdptop;
506 disp_info = &dpu_enc->disp_info;
507
508 if (disp_info->intf_type != INTF_DSI)
509 return;
510
511 /**
512 * disable split modes since encoder will be operating in as the only
513 * encoder, either for the entire use case in the case of, for example,
514 * single DSI, or for this frame in the case of left/right only partial
515 * update.
516 */
517 if (phys_enc->split_role == ENC_ROLE_SOLO) {
518 if (hw_mdptop->ops.setup_split_pipe)
519 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
520 return;
521 }
522
523 cfg.en = true;
524 cfg.mode = phys_enc->intf_mode;
525 cfg.intf = interface;
526
527 if (cfg.en && phys_enc->ops.needs_single_flush &&
528 phys_enc->ops.needs_single_flush(phys_enc))
529 cfg.split_flush_en = true;
530
531 if (phys_enc->split_role == ENC_ROLE_MASTER) {
532 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
533
534 if (hw_mdptop->ops.setup_split_pipe)
535 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
536 }
537 }
538
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)539 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
540 {
541 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
542 int i, intf_count = 0, num_dsc = 0;
543
544 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
545 if (dpu_enc->phys_encs[i])
546 intf_count++;
547
548 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
549 if (dpu_enc->dsc)
550 num_dsc = 2;
551
552 return (num_dsc > 0) && (num_dsc > intf_count);
553 }
554
dpu_encoder_get_dsc_config(struct drm_encoder * drm_enc)555 static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
556 {
557 struct msm_drm_private *priv = drm_enc->dev->dev_private;
558 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
559 int index = dpu_enc->disp_info.h_tile_instance[0];
560
561 if (dpu_enc->disp_info.intf_type == INTF_DSI)
562 return msm_dsi_get_dsc_config(priv->dsi[index]);
563
564 return NULL;
565 }
566
dpu_encoder_get_topology(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct drm_display_mode * mode,struct drm_crtc_state * crtc_state,struct drm_dsc_config * dsc)567 static struct msm_display_topology dpu_encoder_get_topology(
568 struct dpu_encoder_virt *dpu_enc,
569 struct dpu_kms *dpu_kms,
570 struct drm_display_mode *mode,
571 struct drm_crtc_state *crtc_state,
572 struct drm_dsc_config *dsc)
573 {
574 struct msm_display_topology topology = {0};
575 int i, intf_count = 0;
576
577 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
578 if (dpu_enc->phys_encs[i])
579 intf_count++;
580
581 /* Datapath topology selection
582 *
583 * Dual display
584 * 2 LM, 2 INTF ( Split display using 2 interfaces)
585 *
586 * Single display
587 * 1 LM, 1 INTF
588 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
589 *
590 * Add dspps to the reservation requirements if ctm is requested
591 */
592 if (intf_count == 2)
593 topology.num_lm = 2;
594 else if (!dpu_kms->catalog->caps->has_3d_merge)
595 topology.num_lm = 1;
596 else
597 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
598
599 if (crtc_state->ctm)
600 topology.num_dspp = topology.num_lm;
601
602 topology.num_intf = intf_count;
603
604 if (dsc) {
605 /*
606 * In case of Display Stream Compression (DSC), we would use
607 * 2 DSC encoders, 2 layer mixers and 1 interface
608 * this is power optimal and can drive up to (including) 4k
609 * screens
610 */
611 topology.num_dsc = 2;
612 topology.num_lm = 2;
613 topology.num_intf = 1;
614 }
615
616 return topology;
617 }
618
dpu_encoder_virt_atomic_check(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)619 static int dpu_encoder_virt_atomic_check(
620 struct drm_encoder *drm_enc,
621 struct drm_crtc_state *crtc_state,
622 struct drm_connector_state *conn_state)
623 {
624 struct dpu_encoder_virt *dpu_enc;
625 struct msm_drm_private *priv;
626 struct dpu_kms *dpu_kms;
627 struct drm_display_mode *adj_mode;
628 struct msm_display_topology topology;
629 struct dpu_global_state *global_state;
630 struct drm_dsc_config *dsc;
631 int i = 0;
632 int ret = 0;
633
634 if (!drm_enc || !crtc_state || !conn_state) {
635 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
636 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
637 return -EINVAL;
638 }
639
640 dpu_enc = to_dpu_encoder_virt(drm_enc);
641 DPU_DEBUG_ENC(dpu_enc, "\n");
642
643 priv = drm_enc->dev->dev_private;
644 dpu_kms = to_dpu_kms(priv->kms);
645 adj_mode = &crtc_state->adjusted_mode;
646 global_state = dpu_kms_get_global_state(crtc_state->state);
647 if (IS_ERR(global_state))
648 return PTR_ERR(global_state);
649
650 trace_dpu_enc_atomic_check(DRMID(drm_enc));
651
652 /* perform atomic check on the first physical encoder (master) */
653 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
654 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
655
656 if (phys->ops.atomic_check)
657 ret = phys->ops.atomic_check(phys, crtc_state,
658 conn_state);
659 if (ret) {
660 DPU_ERROR_ENC(dpu_enc,
661 "mode unsupported, phys idx %d\n", i);
662 return ret;
663 }
664 }
665
666 dsc = dpu_encoder_get_dsc_config(drm_enc);
667
668 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);
669
670 /*
671 * Release and Allocate resources on every modeset
672 */
673 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
674 dpu_rm_release(global_state, drm_enc);
675
676 if (crtc_state->enable)
677 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
678 drm_enc, crtc_state, topology);
679 }
680
681 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
682
683 return ret;
684 }
685
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)686 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
687 struct msm_display_info *disp_info)
688 {
689 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
690 struct msm_drm_private *priv;
691 struct dpu_kms *dpu_kms;
692 struct dpu_hw_mdp *hw_mdptop;
693 struct drm_encoder *drm_enc;
694 struct dpu_encoder_phys *phys_enc;
695 int i;
696
697 if (!dpu_enc || !disp_info) {
698 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
699 dpu_enc != NULL, disp_info != NULL);
700 return;
701 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
702 DPU_ERROR("invalid num phys enc %d/%d\n",
703 dpu_enc->num_phys_encs,
704 (int) ARRAY_SIZE(dpu_enc->hw_pp));
705 return;
706 }
707
708 drm_enc = &dpu_enc->base;
709 /* this pointers are checked in virt_enable_helper */
710 priv = drm_enc->dev->dev_private;
711
712 dpu_kms = to_dpu_kms(priv->kms);
713 hw_mdptop = dpu_kms->hw_mdp;
714 if (!hw_mdptop) {
715 DPU_ERROR("invalid mdptop\n");
716 return;
717 }
718
719 if (hw_mdptop->ops.setup_vsync_source &&
720 disp_info->is_cmd_mode) {
721 for (i = 0; i < dpu_enc->num_phys_encs; i++)
722 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
723
724 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
725 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
726
727 if (disp_info->is_te_using_watchdog_timer)
728 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
729 else
730 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
731
732 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
733
734 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
735 phys_enc = dpu_enc->phys_encs[i];
736
737 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
738 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
739 vsync_cfg.vsync_source);
740 }
741 }
742 }
743
_dpu_encoder_irq_control(struct drm_encoder * drm_enc,bool enable)744 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
745 {
746 struct dpu_encoder_virt *dpu_enc;
747 int i;
748
749 if (!drm_enc) {
750 DPU_ERROR("invalid encoder\n");
751 return;
752 }
753
754 dpu_enc = to_dpu_encoder_virt(drm_enc);
755
756 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
757 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
758 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
759
760 if (phys->ops.irq_control)
761 phys->ops.irq_control(phys, enable);
762 }
763
764 }
765
_dpu_encoder_resource_control_helper(struct drm_encoder * drm_enc,bool enable)766 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
767 bool enable)
768 {
769 struct msm_drm_private *priv;
770 struct dpu_kms *dpu_kms;
771 struct dpu_encoder_virt *dpu_enc;
772
773 dpu_enc = to_dpu_encoder_virt(drm_enc);
774 priv = drm_enc->dev->dev_private;
775 dpu_kms = to_dpu_kms(priv->kms);
776
777 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
778
779 if (!dpu_enc->cur_master) {
780 DPU_ERROR("encoder master not set\n");
781 return;
782 }
783
784 if (enable) {
785 /* enable DPU core clks */
786 pm_runtime_get_sync(&dpu_kms->pdev->dev);
787
788 /* enable all the irq */
789 _dpu_encoder_irq_control(drm_enc, true);
790
791 } else {
792 /* disable all the irq */
793 _dpu_encoder_irq_control(drm_enc, false);
794
795 /* disable DPU core clks */
796 pm_runtime_put_sync(&dpu_kms->pdev->dev);
797 }
798
799 }
800
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)801 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
802 u32 sw_event)
803 {
804 struct dpu_encoder_virt *dpu_enc;
805 struct msm_drm_private *priv;
806 bool is_vid_mode = false;
807
808 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
809 DPU_ERROR("invalid parameters\n");
810 return -EINVAL;
811 }
812 dpu_enc = to_dpu_encoder_virt(drm_enc);
813 priv = drm_enc->dev->dev_private;
814 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
815
816 /*
817 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
818 * events and return early for other events (ie wb display).
819 */
820 if (!dpu_enc->idle_pc_supported &&
821 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
822 sw_event != DPU_ENC_RC_EVENT_STOP &&
823 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
824 return 0;
825
826 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
827 dpu_enc->rc_state, "begin");
828
829 switch (sw_event) {
830 case DPU_ENC_RC_EVENT_KICKOFF:
831 /* cancel delayed off work, if any */
832 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
833 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
834 sw_event);
835
836 mutex_lock(&dpu_enc->rc_lock);
837
838 /* return if the resource control is already in ON state */
839 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
840 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
841 DRMID(drm_enc), sw_event);
842 mutex_unlock(&dpu_enc->rc_lock);
843 return 0;
844 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
845 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
846 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
847 DRMID(drm_enc), sw_event,
848 dpu_enc->rc_state);
849 mutex_unlock(&dpu_enc->rc_lock);
850 return -EINVAL;
851 }
852
853 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
854 _dpu_encoder_irq_control(drm_enc, true);
855 else
856 _dpu_encoder_resource_control_helper(drm_enc, true);
857
858 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
859
860 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
861 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
862 "kickoff");
863
864 mutex_unlock(&dpu_enc->rc_lock);
865 break;
866
867 case DPU_ENC_RC_EVENT_FRAME_DONE:
868 /*
869 * mutex lock is not used as this event happens at interrupt
870 * context. And locking is not required as, the other events
871 * like KICKOFF and STOP does a wait-for-idle before executing
872 * the resource_control
873 */
874 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
875 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
876 DRMID(drm_enc), sw_event,
877 dpu_enc->rc_state);
878 return -EINVAL;
879 }
880
881 /*
882 * schedule off work item only when there are no
883 * frames pending
884 */
885 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
886 DRM_DEBUG_KMS("id:%d skip schedule work\n",
887 DRMID(drm_enc));
888 return 0;
889 }
890
891 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
892 msecs_to_jiffies(dpu_enc->idle_timeout));
893
894 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
895 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
896 "frame done");
897 break;
898
899 case DPU_ENC_RC_EVENT_PRE_STOP:
900 /* cancel delayed off work, if any */
901 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
902 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
903 sw_event);
904
905 mutex_lock(&dpu_enc->rc_lock);
906
907 if (is_vid_mode &&
908 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
909 _dpu_encoder_irq_control(drm_enc, true);
910 }
911 /* skip if is already OFF or IDLE, resources are off already */
912 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
913 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
914 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
915 DRMID(drm_enc), sw_event,
916 dpu_enc->rc_state);
917 mutex_unlock(&dpu_enc->rc_lock);
918 return 0;
919 }
920
921 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
922
923 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
924 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
925 "pre stop");
926
927 mutex_unlock(&dpu_enc->rc_lock);
928 break;
929
930 case DPU_ENC_RC_EVENT_STOP:
931 mutex_lock(&dpu_enc->rc_lock);
932
933 /* return if the resource control is already in OFF state */
934 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
935 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
936 DRMID(drm_enc), sw_event);
937 mutex_unlock(&dpu_enc->rc_lock);
938 return 0;
939 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
940 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
941 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
942 mutex_unlock(&dpu_enc->rc_lock);
943 return -EINVAL;
944 }
945
946 /**
947 * expect to arrive here only if in either idle state or pre-off
948 * and in IDLE state the resources are already disabled
949 */
950 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
951 _dpu_encoder_resource_control_helper(drm_enc, false);
952
953 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
954
955 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
956 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
957 "stop");
958
959 mutex_unlock(&dpu_enc->rc_lock);
960 break;
961
962 case DPU_ENC_RC_EVENT_ENTER_IDLE:
963 mutex_lock(&dpu_enc->rc_lock);
964
965 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
966 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
967 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
968 mutex_unlock(&dpu_enc->rc_lock);
969 return 0;
970 }
971
972 /*
973 * if we are in ON but a frame was just kicked off,
974 * ignore the IDLE event, it's probably a stale timer event
975 */
976 if (dpu_enc->frame_busy_mask[0]) {
977 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
978 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
979 mutex_unlock(&dpu_enc->rc_lock);
980 return 0;
981 }
982
983 if (is_vid_mode)
984 _dpu_encoder_irq_control(drm_enc, false);
985 else
986 _dpu_encoder_resource_control_helper(drm_enc, false);
987
988 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
989
990 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
991 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
992 "idle");
993
994 mutex_unlock(&dpu_enc->rc_lock);
995 break;
996
997 default:
998 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
999 sw_event);
1000 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1001 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1002 "error");
1003 break;
1004 }
1005
1006 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1007 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1008 "end");
1009 return 0;
1010 }
1011
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1012 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
1013 struct drm_writeback_job *job)
1014 {
1015 struct dpu_encoder_virt *dpu_enc;
1016 int i;
1017
1018 dpu_enc = to_dpu_encoder_virt(drm_enc);
1019
1020 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1021 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1022
1023 if (phys->ops.prepare_wb_job)
1024 phys->ops.prepare_wb_job(phys, job);
1025
1026 }
1027 }
1028
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1029 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1030 struct drm_writeback_job *job)
1031 {
1032 struct dpu_encoder_virt *dpu_enc;
1033 int i;
1034
1035 dpu_enc = to_dpu_encoder_virt(drm_enc);
1036
1037 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1038 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1039
1040 if (phys->ops.cleanup_wb_job)
1041 phys->ops.cleanup_wb_job(phys, job);
1042
1043 }
1044 }
1045
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1046 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1047 struct drm_crtc_state *crtc_state,
1048 struct drm_connector_state *conn_state)
1049 {
1050 struct dpu_encoder_virt *dpu_enc;
1051 struct msm_drm_private *priv;
1052 struct dpu_kms *dpu_kms;
1053 struct dpu_crtc_state *cstate;
1054 struct dpu_global_state *global_state;
1055 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1056 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1057 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
1058 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
1059 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1060 int num_lm, num_ctl, num_pp, num_dsc;
1061 unsigned int dsc_mask = 0;
1062 int i;
1063
1064 if (!drm_enc) {
1065 DPU_ERROR("invalid encoder\n");
1066 return;
1067 }
1068
1069 dpu_enc = to_dpu_encoder_virt(drm_enc);
1070 DPU_DEBUG_ENC(dpu_enc, "\n");
1071
1072 priv = drm_enc->dev->dev_private;
1073 dpu_kms = to_dpu_kms(priv->kms);
1074
1075 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1076 if (IS_ERR_OR_NULL(global_state)) {
1077 DPU_ERROR("Failed to get global state");
1078 return;
1079 }
1080
1081 trace_dpu_enc_mode_set(DRMID(drm_enc));
1082
1083 /* Query resource that have been reserved in atomic check step. */
1084 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1085 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1086 ARRAY_SIZE(hw_pp));
1087 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1088 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1089 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1090 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1091 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1092 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1093 ARRAY_SIZE(hw_dspp));
1094
1095 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1096 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1097 : NULL;
1098
1099 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1100 drm_enc->base.id, DPU_HW_BLK_DSC,
1101 hw_dsc, ARRAY_SIZE(hw_dsc));
1102 for (i = 0; i < num_dsc; i++) {
1103 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1104 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1105 }
1106
1107 dpu_enc->dsc_mask = dsc_mask;
1108
1109 cstate = to_dpu_crtc_state(crtc_state);
1110
1111 for (i = 0; i < num_lm; i++) {
1112 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1113
1114 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1115 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1116 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1117 }
1118
1119 cstate->num_mixers = num_lm;
1120
1121 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1122 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1123
1124 phys->hw_pp = dpu_enc->hw_pp[i];
1125 if (!phys->hw_pp) {
1126 DPU_ERROR_ENC(dpu_enc,
1127 "no pp block assigned at idx: %d\n", i);
1128 return;
1129 }
1130
1131 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
1132 if (!phys->hw_ctl) {
1133 DPU_ERROR_ENC(dpu_enc,
1134 "no ctl block assigned at idx: %d\n", i);
1135 return;
1136 }
1137
1138 phys->cached_mode = crtc_state->adjusted_mode;
1139 if (phys->ops.atomic_mode_set)
1140 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1141 }
1142 }
1143
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1144 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1145 {
1146 struct dpu_encoder_virt *dpu_enc = NULL;
1147 int i;
1148
1149 if (!drm_enc || !drm_enc->dev) {
1150 DPU_ERROR("invalid parameters\n");
1151 return;
1152 }
1153
1154 dpu_enc = to_dpu_encoder_virt(drm_enc);
1155 if (!dpu_enc || !dpu_enc->cur_master) {
1156 DPU_ERROR("invalid dpu encoder/master\n");
1157 return;
1158 }
1159
1160
1161 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1162 dpu_enc->cur_master->hw_mdptop &&
1163 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1164 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1165 dpu_enc->cur_master->hw_mdptop);
1166
1167 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1168
1169 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1170 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1171 unsigned bpc = dpu_enc->connector->display_info.bpc;
1172 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1173 if (!dpu_enc->hw_pp[i])
1174 continue;
1175 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1176 }
1177 }
1178 }
1179
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1180 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1181 {
1182 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1183
1184 mutex_lock(&dpu_enc->enc_lock);
1185
1186 if (!dpu_enc->enabled)
1187 goto out;
1188
1189 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1190 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1191 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1192 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1193
1194 _dpu_encoder_virt_enable_helper(drm_enc);
1195
1196 out:
1197 mutex_unlock(&dpu_enc->enc_lock);
1198 }
1199
dpu_encoder_virt_atomic_enable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1200 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
1201 struct drm_atomic_state *state)
1202 {
1203 struct dpu_encoder_virt *dpu_enc = NULL;
1204 int ret = 0;
1205 struct drm_display_mode *cur_mode = NULL;
1206
1207 dpu_enc = to_dpu_encoder_virt(drm_enc);
1208
1209 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1210
1211 mutex_lock(&dpu_enc->enc_lock);
1212
1213 dpu_enc->commit_done_timedout = false;
1214
1215 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1216
1217 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1218
1219 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1220 cur_mode->vdisplay);
1221
1222 /* always enable slave encoder before master */
1223 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1224 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1225
1226 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1227 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1228
1229 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1230 if (ret) {
1231 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1232 ret);
1233 goto out;
1234 }
1235
1236 _dpu_encoder_virt_enable_helper(drm_enc);
1237
1238 dpu_enc->enabled = true;
1239
1240 out:
1241 mutex_unlock(&dpu_enc->enc_lock);
1242 }
1243
dpu_encoder_virt_atomic_disable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1244 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
1245 struct drm_atomic_state *state)
1246 {
1247 struct dpu_encoder_virt *dpu_enc = NULL;
1248 struct drm_crtc *crtc;
1249 struct drm_crtc_state *old_state = NULL;
1250 int i = 0;
1251
1252 dpu_enc = to_dpu_encoder_virt(drm_enc);
1253 DPU_DEBUG_ENC(dpu_enc, "\n");
1254
1255 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
1256 if (crtc)
1257 old_state = drm_atomic_get_old_crtc_state(state, crtc);
1258
1259 /*
1260 * The encoder is already disabled if self refresh mode was set earlier,
1261 * in the old_state for the corresponding crtc.
1262 */
1263 if (old_state && old_state->self_refresh_active)
1264 return;
1265
1266 mutex_lock(&dpu_enc->enc_lock);
1267 dpu_enc->enabled = false;
1268
1269 trace_dpu_enc_disable(DRMID(drm_enc));
1270
1271 /* wait for idle */
1272 dpu_encoder_wait_for_tx_complete(drm_enc);
1273
1274 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1275
1276 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1277 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1278
1279 if (phys->ops.disable)
1280 phys->ops.disable(phys);
1281 }
1282
1283
1284 /* after phys waits for frame-done, should be no more frames pending */
1285 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1286 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1287 del_timer_sync(&dpu_enc->frame_done_timer);
1288 }
1289
1290 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1291
1292 dpu_enc->connector = NULL;
1293
1294 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1295
1296 mutex_unlock(&dpu_enc->enc_lock);
1297 }
1298
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,struct dpu_rm * dpu_rm,enum dpu_intf_type type,u32 controller_id)1299 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1300 struct dpu_rm *dpu_rm,
1301 enum dpu_intf_type type, u32 controller_id)
1302 {
1303 int i = 0;
1304
1305 if (type == INTF_WB)
1306 return NULL;
1307
1308 for (i = 0; i < catalog->intf_count; i++) {
1309 if (catalog->intf[i].type == type
1310 && catalog->intf[i].controller_id == controller_id) {
1311 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
1312 }
1313 }
1314
1315 return NULL;
1316 }
1317
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1318 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1319 struct dpu_encoder_phys *phy_enc)
1320 {
1321 struct dpu_encoder_virt *dpu_enc = NULL;
1322 unsigned long lock_flags;
1323
1324 if (!drm_enc || !phy_enc)
1325 return;
1326
1327 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1328 dpu_enc = to_dpu_encoder_virt(drm_enc);
1329
1330 atomic_inc(&phy_enc->vsync_cnt);
1331
1332 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1333 if (dpu_enc->crtc)
1334 dpu_crtc_vblank_callback(dpu_enc->crtc);
1335 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1336
1337 DPU_ATRACE_END("encoder_vblank_callback");
1338 }
1339
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1340 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1341 struct dpu_encoder_phys *phy_enc)
1342 {
1343 if (!phy_enc)
1344 return;
1345
1346 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1347 atomic_inc(&phy_enc->underrun_cnt);
1348
1349 /* trigger dump only on the first underrun */
1350 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1351 msm_disp_snapshot_state(drm_enc->dev);
1352
1353 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1354 atomic_read(&phy_enc->underrun_cnt));
1355 DPU_ATRACE_END("encoder_underrun_callback");
1356 }
1357
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1358 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1359 {
1360 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1361 unsigned long lock_flags;
1362
1363 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1364 /* crtc should always be cleared before re-assigning */
1365 WARN_ON(crtc && dpu_enc->crtc);
1366 dpu_enc->crtc = crtc;
1367 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1368 }
1369
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1370 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1371 struct drm_crtc *crtc, bool enable)
1372 {
1373 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1374 unsigned long lock_flags;
1375 int i;
1376
1377 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1378
1379 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1380 if (dpu_enc->crtc != crtc) {
1381 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1382 return;
1383 }
1384 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1385
1386 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1387 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1388
1389 if (phys->ops.control_vblank_irq)
1390 phys->ops.control_vblank_irq(phys, enable);
1391 }
1392 }
1393
dpu_encoder_register_frame_event_callback(struct drm_encoder * drm_enc,void (* frame_event_cb)(void *,u32 event),void * frame_event_cb_data)1394 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1395 void (*frame_event_cb)(void *, u32 event),
1396 void *frame_event_cb_data)
1397 {
1398 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1399 unsigned long lock_flags;
1400 bool enable;
1401
1402 enable = frame_event_cb ? true : false;
1403
1404 if (!drm_enc) {
1405 DPU_ERROR("invalid encoder\n");
1406 return;
1407 }
1408 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1409
1410 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1411 dpu_enc->crtc_frame_event_cb = frame_event_cb;
1412 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1413 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1414 }
1415
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1416 void dpu_encoder_frame_done_callback(
1417 struct drm_encoder *drm_enc,
1418 struct dpu_encoder_phys *ready_phys, u32 event)
1419 {
1420 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1421 unsigned int i;
1422
1423 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1424 | DPU_ENCODER_FRAME_EVENT_ERROR
1425 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1426
1427 if (!dpu_enc->frame_busy_mask[0]) {
1428 /**
1429 * suppress frame_done without waiter,
1430 * likely autorefresh
1431 */
1432 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1433 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1434 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
1435 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
1436 return;
1437 }
1438
1439 /* One of the physical encoders has become idle */
1440 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1441 if (dpu_enc->phys_encs[i] == ready_phys) {
1442 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1443 dpu_enc->frame_busy_mask[0]);
1444 clear_bit(i, dpu_enc->frame_busy_mask);
1445 }
1446 }
1447
1448 if (!dpu_enc->frame_busy_mask[0]) {
1449 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1450 del_timer(&dpu_enc->frame_done_timer);
1451
1452 dpu_encoder_resource_control(drm_enc,
1453 DPU_ENC_RC_EVENT_FRAME_DONE);
1454
1455 if (dpu_enc->crtc_frame_event_cb)
1456 dpu_enc->crtc_frame_event_cb(
1457 dpu_enc->crtc_frame_event_cb_data,
1458 event);
1459 }
1460 } else {
1461 if (dpu_enc->crtc_frame_event_cb)
1462 dpu_enc->crtc_frame_event_cb(
1463 dpu_enc->crtc_frame_event_cb_data, event);
1464 }
1465 }
1466
dpu_encoder_off_work(struct work_struct * work)1467 static void dpu_encoder_off_work(struct work_struct *work)
1468 {
1469 struct dpu_encoder_virt *dpu_enc = container_of(work,
1470 struct dpu_encoder_virt, delayed_off_work.work);
1471
1472 dpu_encoder_resource_control(&dpu_enc->base,
1473 DPU_ENC_RC_EVENT_ENTER_IDLE);
1474
1475 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1476 DPU_ENCODER_FRAME_EVENT_IDLE);
1477 }
1478
1479 /**
1480 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1481 * @drm_enc: Pointer to drm encoder structure
1482 * @phys: Pointer to physical encoder structure
1483 * @extra_flush_bits: Additional bit mask to include in flush trigger
1484 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1485 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1486 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1487 {
1488 struct dpu_hw_ctl *ctl;
1489 int pending_kickoff_cnt;
1490 u32 ret = UINT_MAX;
1491
1492 if (!phys->hw_pp) {
1493 DPU_ERROR("invalid pingpong hw\n");
1494 return;
1495 }
1496
1497 ctl = phys->hw_ctl;
1498 if (!ctl->ops.trigger_flush) {
1499 DPU_ERROR("missing trigger cb\n");
1500 return;
1501 }
1502
1503 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1504
1505 if (extra_flush_bits && ctl->ops.update_pending_flush)
1506 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1507
1508 ctl->ops.trigger_flush(ctl);
1509
1510 if (ctl->ops.get_pending_flush)
1511 ret = ctl->ops.get_pending_flush(ctl);
1512
1513 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1514 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1515 phys->hw_intf ? phys->hw_intf->idx : -1,
1516 phys->hw_wb ? phys->hw_wb->idx : -1,
1517 pending_kickoff_cnt, ctl->idx,
1518 extra_flush_bits, ret);
1519 }
1520
1521 /**
1522 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1523 * @phys: Pointer to physical encoder structure
1524 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1525 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1526 {
1527 if (!phys) {
1528 DPU_ERROR("invalid argument(s)\n");
1529 return;
1530 }
1531
1532 if (!phys->hw_pp) {
1533 DPU_ERROR("invalid pingpong hw\n");
1534 return;
1535 }
1536
1537 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1538 phys->ops.trigger_start(phys);
1539 }
1540
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1541 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1542 {
1543 struct dpu_hw_ctl *ctl;
1544
1545 ctl = phys_enc->hw_ctl;
1546 if (ctl->ops.trigger_start) {
1547 ctl->ops.trigger_start(ctl);
1548 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1549 }
1550 }
1551
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,u32 irq_idx,struct dpu_encoder_wait_info * info)1552 static int dpu_encoder_helper_wait_event_timeout(
1553 int32_t drm_id,
1554 u32 irq_idx,
1555 struct dpu_encoder_wait_info *info)
1556 {
1557 int rc = 0;
1558 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1559 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1560 s64 time;
1561
1562 do {
1563 rc = wait_event_timeout(*(info->wq),
1564 atomic_read(info->atomic_cnt) == 0, jiffies);
1565 time = ktime_to_ms(ktime_get());
1566
1567 trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1568 expected_time,
1569 atomic_read(info->atomic_cnt));
1570 /* If we timed out, counter is valid and time is less, wait again */
1571 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1572 (time < expected_time));
1573
1574 return rc;
1575 }
1576
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1577 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1578 {
1579 struct dpu_encoder_virt *dpu_enc;
1580 struct dpu_hw_ctl *ctl;
1581 int rc;
1582 struct drm_encoder *drm_enc;
1583
1584 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1585 ctl = phys_enc->hw_ctl;
1586 drm_enc = phys_enc->parent;
1587
1588 if (!ctl->ops.reset)
1589 return;
1590
1591 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1592 ctl->idx);
1593
1594 rc = ctl->ops.reset(ctl);
1595 if (rc) {
1596 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1597 msm_disp_snapshot_state(drm_enc->dev);
1598 }
1599
1600 phys_enc->enable_state = DPU_ENC_ENABLED;
1601 }
1602
1603 /**
1604 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1605 * Iterate through the physical encoders and perform consolidated flush
1606 * and/or control start triggering as needed. This is done in the virtual
1607 * encoder rather than the individual physical ones in order to handle
1608 * use cases that require visibility into multiple physical encoders at
1609 * a time.
1610 * @dpu_enc: Pointer to virtual encoder structure
1611 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1612 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1613 {
1614 struct dpu_hw_ctl *ctl;
1615 uint32_t i, pending_flush;
1616 unsigned long lock_flags;
1617
1618 pending_flush = 0x0;
1619
1620 /* update pending counts and trigger kickoff ctl flush atomically */
1621 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1622
1623 /* don't perform flush/start operations for slave encoders */
1624 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1625 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1626
1627 if (phys->enable_state == DPU_ENC_DISABLED)
1628 continue;
1629
1630 ctl = phys->hw_ctl;
1631
1632 /*
1633 * This is cleared in frame_done worker, which isn't invoked
1634 * for async commits. So don't set this for async, since it'll
1635 * roll over to the next commit.
1636 */
1637 if (phys->split_role != ENC_ROLE_SLAVE)
1638 set_bit(i, dpu_enc->frame_busy_mask);
1639
1640 if (!phys->ops.needs_single_flush ||
1641 !phys->ops.needs_single_flush(phys))
1642 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1643 else if (ctl->ops.get_pending_flush)
1644 pending_flush |= ctl->ops.get_pending_flush(ctl);
1645 }
1646
1647 /* for split flush, combine pending flush masks and send to master */
1648 if (pending_flush && dpu_enc->cur_master) {
1649 _dpu_encoder_trigger_flush(
1650 &dpu_enc->base,
1651 dpu_enc->cur_master,
1652 pending_flush);
1653 }
1654
1655 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1656
1657 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1658 }
1659
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1660 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1661 {
1662 struct dpu_encoder_virt *dpu_enc;
1663 struct dpu_encoder_phys *phys;
1664 unsigned int i;
1665 struct dpu_hw_ctl *ctl;
1666 struct msm_display_info *disp_info;
1667
1668 if (!drm_enc) {
1669 DPU_ERROR("invalid encoder\n");
1670 return;
1671 }
1672 dpu_enc = to_dpu_encoder_virt(drm_enc);
1673 disp_info = &dpu_enc->disp_info;
1674
1675 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1676 phys = dpu_enc->phys_encs[i];
1677
1678 ctl = phys->hw_ctl;
1679 ctl->ops.clear_pending_flush(ctl);
1680
1681 /* update only for command mode primary ctl */
1682 if ((phys == dpu_enc->cur_master) &&
1683 disp_info->is_cmd_mode
1684 && ctl->ops.trigger_pending)
1685 ctl->ops.trigger_pending(ctl);
1686 }
1687 }
1688
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1689 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1690 struct drm_display_mode *mode)
1691 {
1692 u64 pclk_rate;
1693 u32 pclk_period;
1694 u32 line_time;
1695
1696 /*
1697 * For linetime calculation, only operate on master encoder.
1698 */
1699 if (!dpu_enc->cur_master)
1700 return 0;
1701
1702 if (!dpu_enc->cur_master->ops.get_line_count) {
1703 DPU_ERROR("get_line_count function not defined\n");
1704 return 0;
1705 }
1706
1707 pclk_rate = mode->clock; /* pixel clock in kHz */
1708 if (pclk_rate == 0) {
1709 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1710 return 0;
1711 }
1712
1713 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1714 if (pclk_period == 0) {
1715 DPU_ERROR("pclk period is 0\n");
1716 return 0;
1717 }
1718
1719 /*
1720 * Line time calculation based on Pixel clock and HTOTAL.
1721 * Final unit is in ns.
1722 */
1723 line_time = (pclk_period * mode->htotal) / 1000;
1724 if (line_time == 0) {
1725 DPU_ERROR("line time calculation is 0\n");
1726 return 0;
1727 }
1728
1729 DPU_DEBUG_ENC(dpu_enc,
1730 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1731 pclk_rate, pclk_period, line_time);
1732
1733 return line_time;
1734 }
1735
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1736 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1737 {
1738 struct drm_display_mode *mode;
1739 struct dpu_encoder_virt *dpu_enc;
1740 u32 cur_line;
1741 u32 line_time;
1742 u32 vtotal, time_to_vsync;
1743 ktime_t cur_time;
1744
1745 dpu_enc = to_dpu_encoder_virt(drm_enc);
1746
1747 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1748 DPU_ERROR("crtc/crtc state object is NULL\n");
1749 return -EINVAL;
1750 }
1751 mode = &drm_enc->crtc->state->adjusted_mode;
1752
1753 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1754 if (!line_time)
1755 return -EINVAL;
1756
1757 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1758
1759 vtotal = mode->vtotal;
1760 if (cur_line >= vtotal)
1761 time_to_vsync = line_time * vtotal;
1762 else
1763 time_to_vsync = line_time * (vtotal - cur_line);
1764
1765 if (time_to_vsync == 0) {
1766 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1767 vtotal);
1768 return -EINVAL;
1769 }
1770
1771 cur_time = ktime_get();
1772 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1773
1774 DPU_DEBUG_ENC(dpu_enc,
1775 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1776 cur_line, vtotal, time_to_vsync,
1777 ktime_to_ms(cur_time),
1778 ktime_to_ms(*wakeup_time));
1779 return 0;
1780 }
1781
1782 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1783 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1784 u32 enc_ip_width)
1785 {
1786 int ssm_delay, total_pixels, soft_slice_per_enc;
1787
1788 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1789
1790 /*
1791 * minimum number of initial line pixels is a sum of:
1792 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1793 * 91 for 10 bpc) * 3
1794 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1795 * 3. the initial xmit delay
1796 * 4. total pipeline delay through the "lock step" of encoder (47)
1797 * 5. 6 additional pixels as the output of the rate buffer is
1798 * 48 bits wide
1799 */
1800 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1801 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1802 if (soft_slice_per_enc > 1)
1803 total_pixels += (ssm_delay * 3);
1804 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1805 }
1806
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1807 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
1808 struct dpu_hw_dsc *hw_dsc,
1809 struct dpu_hw_pingpong *hw_pp,
1810 struct drm_dsc_config *dsc,
1811 u32 common_mode,
1812 u32 initial_lines)
1813 {
1814 if (hw_dsc->ops.dsc_config)
1815 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1816
1817 if (hw_dsc->ops.dsc_config_thresh)
1818 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1819
1820 if (hw_pp->ops.setup_dsc)
1821 hw_pp->ops.setup_dsc(hw_pp);
1822
1823 if (hw_dsc->ops.dsc_bind_pingpong_blk)
1824 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
1825
1826 if (hw_pp->ops.enable_dsc)
1827 hw_pp->ops.enable_dsc(hw_pp);
1828
1829 if (ctl->ops.update_pending_flush_dsc)
1830 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
1831 }
1832
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)1833 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
1834 struct drm_dsc_config *dsc)
1835 {
1836 /* coding only for 2LM, 2enc, 1 dsc config */
1837 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
1838 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
1839 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
1840 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
1841 int this_frame_slices;
1842 int intf_ip_w, enc_ip_w;
1843 int dsc_common_mode;
1844 int pic_width;
1845 u32 initial_lines;
1846 int i;
1847
1848 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1849 hw_pp[i] = dpu_enc->hw_pp[i];
1850 hw_dsc[i] = dpu_enc->hw_dsc[i];
1851
1852 if (!hw_pp[i] || !hw_dsc[i]) {
1853 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
1854 return;
1855 }
1856 }
1857
1858 dsc_common_mode = 0;
1859 pic_width = dsc->pic_width;
1860
1861 dsc_common_mode = DSC_MODE_SPLIT_PANEL;
1862 if (dpu_encoder_use_dsc_merge(enc_master->parent))
1863 dsc_common_mode |= DSC_MODE_MULTIPLEX;
1864 if (enc_master->intf_mode == INTF_MODE_VIDEO)
1865 dsc_common_mode |= DSC_MODE_VIDEO;
1866
1867 this_frame_slices = pic_width / dsc->slice_width;
1868 intf_ip_w = this_frame_slices * dsc->slice_width;
1869
1870 /*
1871 * dsc merge case: when using 2 encoders for the same stream,
1872 * no. of slices need to be same on both the encoders.
1873 */
1874 enc_ip_w = intf_ip_w / 2;
1875 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
1876
1877 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1878 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
1879 dsc, dsc_common_mode, initial_lines);
1880 }
1881
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)1882 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1883 {
1884 struct dpu_encoder_virt *dpu_enc;
1885 struct dpu_encoder_phys *phys;
1886 bool needs_hw_reset = false;
1887 unsigned int i;
1888
1889 dpu_enc = to_dpu_encoder_virt(drm_enc);
1890
1891 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1892
1893 /* prepare for next kickoff, may include waiting on previous kickoff */
1894 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1895 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1896 phys = dpu_enc->phys_encs[i];
1897 if (phys->ops.prepare_for_kickoff)
1898 phys->ops.prepare_for_kickoff(phys);
1899 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1900 needs_hw_reset = true;
1901 }
1902 DPU_ATRACE_END("enc_prepare_for_kickoff");
1903
1904 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1905
1906 /* if any phys needs reset, reset all phys, in-order */
1907 if (needs_hw_reset) {
1908 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1909 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1910 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1911 }
1912 }
1913
1914 if (dpu_enc->dsc)
1915 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
1916 }
1917
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)1918 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
1919 {
1920 struct dpu_encoder_virt *dpu_enc;
1921 unsigned int i;
1922 struct dpu_encoder_phys *phys;
1923
1924 dpu_enc = to_dpu_encoder_virt(drm_enc);
1925
1926 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1927 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1928 phys = dpu_enc->phys_encs[i];
1929 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
1930 DPU_DEBUG("invalid FB not kicking off\n");
1931 return false;
1932 }
1933 }
1934 }
1935
1936 return true;
1937 }
1938
dpu_encoder_kickoff(struct drm_encoder * drm_enc)1939 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1940 {
1941 struct dpu_encoder_virt *dpu_enc;
1942 struct dpu_encoder_phys *phys;
1943 unsigned long timeout_ms;
1944 unsigned int i;
1945
1946 DPU_ATRACE_BEGIN("encoder_kickoff");
1947 dpu_enc = to_dpu_encoder_virt(drm_enc);
1948
1949 trace_dpu_enc_kickoff(DRMID(drm_enc));
1950
1951 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1952 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1953
1954 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1955 mod_timer(&dpu_enc->frame_done_timer,
1956 jiffies + msecs_to_jiffies(timeout_ms));
1957
1958 /* All phys encs are ready to go, trigger the kickoff */
1959 _dpu_encoder_kickoff_phys(dpu_enc);
1960
1961 /* allow phys encs to handle any post-kickoff business */
1962 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1963 phys = dpu_enc->phys_encs[i];
1964 if (phys->ops.handle_post_kickoff)
1965 phys->ops.handle_post_kickoff(phys);
1966 }
1967
1968 DPU_ATRACE_END("encoder_kickoff");
1969 }
1970
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)1971 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
1972 {
1973 struct dpu_hw_mixer_cfg mixer;
1974 int i, num_lm;
1975 struct dpu_global_state *global_state;
1976 struct dpu_hw_blk *hw_lm[2];
1977 struct dpu_hw_mixer *hw_mixer[2];
1978 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
1979
1980 memset(&mixer, 0, sizeof(mixer));
1981
1982 /* reset all mixers for this encoder */
1983 if (phys_enc->hw_ctl->ops.clear_all_blendstages)
1984 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
1985
1986 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
1987
1988 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
1989 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1990
1991 for (i = 0; i < num_lm; i++) {
1992 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
1993 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer)
1994 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
1995
1996 /* clear all blendstages */
1997 if (phys_enc->hw_ctl->ops.setup_blendstage)
1998 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
1999 }
2000 }
2001
dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp)2002 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2003 struct dpu_hw_dsc *hw_dsc,
2004 struct dpu_hw_pingpong *hw_pp)
2005 {
2006 if (hw_dsc->ops.dsc_disable)
2007 hw_dsc->ops.dsc_disable(hw_dsc);
2008
2009 if (hw_pp->ops.disable_dsc)
2010 hw_pp->ops.disable_dsc(hw_pp);
2011
2012 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2013 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
2014
2015 if (ctl->ops.update_pending_flush_dsc)
2016 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2017 }
2018
dpu_encoder_unprep_dsc(struct dpu_encoder_virt * dpu_enc)2019 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2020 {
2021 /* coding only for 2LM, 2enc, 1 dsc config */
2022 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2023 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2024 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2025 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2026 int i;
2027
2028 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2029 hw_pp[i] = dpu_enc->hw_pp[i];
2030 hw_dsc[i] = dpu_enc->hw_dsc[i];
2031
2032 if (hw_pp[i] && hw_dsc[i])
2033 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2034 }
2035 }
2036
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2037 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2038 {
2039 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2040 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2041 int i;
2042 struct dpu_encoder_virt *dpu_enc;
2043
2044 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2045
2046 phys_enc->hw_ctl->ops.reset(ctl);
2047
2048 dpu_encoder_helper_reset_mixers(phys_enc);
2049
2050 /*
2051 * TODO: move the once-only operation like CTL flush/trigger
2052 * into dpu_encoder_virt_disable() and all operations which need
2053 * to be done per phys encoder into the phys_disable() op.
2054 */
2055 if (phys_enc->hw_wb) {
2056 /* disable the PP block */
2057 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2058 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE);
2059
2060 /* mark WB flush as pending */
2061 if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
2062 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2063 } else {
2064 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2065 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2066 phys_enc->hw_intf->ops.bind_pingpong_blk(
2067 dpu_enc->phys_encs[i]->hw_intf,
2068 PINGPONG_NONE);
2069
2070 /* mark INTF flush as pending */
2071 if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
2072 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
2073 dpu_enc->phys_encs[i]->hw_intf->idx);
2074 }
2075 }
2076
2077 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2078 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2079
2080 /* reset the merge 3D HW block */
2081 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2082 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2083 BLEND_3D_NONE);
2084 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
2085 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2086 phys_enc->hw_pp->merge_3d->idx);
2087 }
2088
2089 if (dpu_enc->dsc) {
2090 dpu_encoder_unprep_dsc(dpu_enc);
2091 dpu_enc->dsc = NULL;
2092 }
2093
2094 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2095 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2096 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
2097
2098 if (phys_enc->hw_intf)
2099 intf_cfg.intf = phys_enc->hw_intf->idx;
2100 if (phys_enc->hw_wb)
2101 intf_cfg.wb = phys_enc->hw_wb->idx;
2102
2103 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2104 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2105
2106 if (ctl->ops.reset_intf_cfg)
2107 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2108
2109 ctl->ops.trigger_flush(ctl);
2110 ctl->ops.trigger_start(ctl);
2111 ctl->ops.clear_pending_flush(ctl);
2112 }
2113
2114 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2115 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2116 {
2117 struct dpu_encoder_virt *dpu_enc = s->private;
2118 int i;
2119
2120 mutex_lock(&dpu_enc->enc_lock);
2121 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2122 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2123
2124 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d ",
2125 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
2126 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
2127 atomic_read(&phys->vsync_cnt),
2128 atomic_read(&phys->underrun_cnt));
2129
2130 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2131 }
2132 mutex_unlock(&dpu_enc->enc_lock);
2133
2134 return 0;
2135 }
2136
2137 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2138
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2139 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2140 {
2141 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2142
2143 char name[12];
2144
2145 if (!drm_enc->dev) {
2146 DPU_ERROR("invalid encoder or kms\n");
2147 return -EINVAL;
2148 }
2149
2150 snprintf(name, sizeof(name), "encoder%u", drm_enc->base.id);
2151
2152 /* create overall sub-directory for the encoder */
2153 dpu_enc->debugfs_root = debugfs_create_dir(name,
2154 drm_enc->dev->primary->debugfs_root);
2155
2156 /* don't error check these */
2157 debugfs_create_file("status", 0600,
2158 dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
2159
2160 return 0;
2161 }
2162 #else
_dpu_encoder_init_debugfs(struct drm_encoder * drm_enc)2163 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
2164 {
2165 return 0;
2166 }
2167 #endif
2168
dpu_encoder_late_register(struct drm_encoder * encoder)2169 static int dpu_encoder_late_register(struct drm_encoder *encoder)
2170 {
2171 return _dpu_encoder_init_debugfs(encoder);
2172 }
2173
dpu_encoder_early_unregister(struct drm_encoder * encoder)2174 static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
2175 {
2176 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2177
2178 debugfs_remove_recursive(dpu_enc->debugfs_root);
2179 }
2180
dpu_encoder_virt_add_phys_encs(struct drm_device * dev,struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2181 static int dpu_encoder_virt_add_phys_encs(
2182 struct drm_device *dev,
2183 struct msm_display_info *disp_info,
2184 struct dpu_encoder_virt *dpu_enc,
2185 struct dpu_enc_phys_init_params *params)
2186 {
2187 struct dpu_encoder_phys *enc = NULL;
2188
2189 DPU_DEBUG_ENC(dpu_enc, "\n");
2190
2191 /*
2192 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2193 * in this function, check up-front.
2194 */
2195 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2196 ARRAY_SIZE(dpu_enc->phys_encs)) {
2197 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2198 dpu_enc->num_phys_encs);
2199 return -EINVAL;
2200 }
2201
2202
2203 if (disp_info->intf_type == INTF_WB) {
2204 enc = dpu_encoder_phys_wb_init(dev, params);
2205
2206 if (IS_ERR(enc)) {
2207 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2208 PTR_ERR(enc));
2209 return PTR_ERR(enc);
2210 }
2211
2212 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2213 ++dpu_enc->num_phys_encs;
2214 } else if (disp_info->is_cmd_mode) {
2215 enc = dpu_encoder_phys_cmd_init(dev, params);
2216
2217 if (IS_ERR(enc)) {
2218 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2219 PTR_ERR(enc));
2220 return PTR_ERR(enc);
2221 }
2222
2223 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2224 ++dpu_enc->num_phys_encs;
2225 } else {
2226 enc = dpu_encoder_phys_vid_init(dev, params);
2227
2228 if (IS_ERR(enc)) {
2229 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2230 PTR_ERR(enc));
2231 return PTR_ERR(enc);
2232 }
2233
2234 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2235 ++dpu_enc->num_phys_encs;
2236 }
2237
2238 if (params->split_role == ENC_ROLE_SLAVE)
2239 dpu_enc->cur_slave = enc;
2240 else
2241 dpu_enc->cur_master = enc;
2242
2243 return 0;
2244 }
2245
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2246 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2247 struct dpu_kms *dpu_kms,
2248 struct msm_display_info *disp_info)
2249 {
2250 int ret = 0;
2251 int i = 0;
2252 struct dpu_enc_phys_init_params phys_params;
2253
2254 if (!dpu_enc) {
2255 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2256 return -EINVAL;
2257 }
2258
2259 dpu_enc->cur_master = NULL;
2260
2261 memset(&phys_params, 0, sizeof(phys_params));
2262 phys_params.dpu_kms = dpu_kms;
2263 phys_params.parent = &dpu_enc->base;
2264 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2265
2266 WARN_ON(disp_info->num_of_h_tiles < 1);
2267
2268 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2269
2270 if (disp_info->intf_type != INTF_WB)
2271 dpu_enc->idle_pc_supported =
2272 dpu_kms->catalog->caps->has_idle_pc;
2273
2274 mutex_lock(&dpu_enc->enc_lock);
2275 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2276 /*
2277 * Left-most tile is at index 0, content is controller id
2278 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2279 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2280 */
2281 u32 controller_id = disp_info->h_tile_instance[i];
2282
2283 if (disp_info->num_of_h_tiles > 1) {
2284 if (i == 0)
2285 phys_params.split_role = ENC_ROLE_MASTER;
2286 else
2287 phys_params.split_role = ENC_ROLE_SLAVE;
2288 } else {
2289 phys_params.split_role = ENC_ROLE_SOLO;
2290 }
2291
2292 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2293 i, controller_id, phys_params.split_role);
2294
2295 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
2296 disp_info->intf_type,
2297 controller_id);
2298
2299 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
2300 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
2301
2302 if (!phys_params.hw_intf && !phys_params.hw_wb) {
2303 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2304 ret = -EINVAL;
2305 break;
2306 }
2307
2308 if (phys_params.hw_intf && phys_params.hw_wb) {
2309 DPU_ERROR_ENC(dpu_enc,
2310 "invalid phys both intf and wb block at idx: %d\n", i);
2311 ret = -EINVAL;
2312 break;
2313 }
2314
2315 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,
2316 dpu_enc, &phys_params);
2317 if (ret) {
2318 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2319 break;
2320 }
2321 }
2322
2323 mutex_unlock(&dpu_enc->enc_lock);
2324
2325 return ret;
2326 }
2327
dpu_encoder_frame_done_timeout(struct timer_list * t)2328 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2329 {
2330 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2331 frame_done_timer);
2332 struct drm_encoder *drm_enc = &dpu_enc->base;
2333 u32 event;
2334
2335 if (!drm_enc->dev) {
2336 DPU_ERROR("invalid parameters\n");
2337 return;
2338 }
2339
2340 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2341 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2342 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2343 return;
2344 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2345 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2346 return;
2347 }
2348
2349 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2350
2351 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2352 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2353 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2354 }
2355
2356 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2357 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2358 .atomic_disable = dpu_encoder_virt_atomic_disable,
2359 .atomic_enable = dpu_encoder_virt_atomic_enable,
2360 .atomic_check = dpu_encoder_virt_atomic_check,
2361 };
2362
2363 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2364 .destroy = dpu_encoder_destroy,
2365 .late_register = dpu_encoder_late_register,
2366 .early_unregister = dpu_encoder_early_unregister,
2367 };
2368
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode,struct msm_display_info * disp_info)2369 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2370 int drm_enc_mode,
2371 struct msm_display_info *disp_info)
2372 {
2373 struct msm_drm_private *priv = dev->dev_private;
2374 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2375 struct drm_encoder *drm_enc = NULL;
2376 struct dpu_encoder_virt *dpu_enc = NULL;
2377 int ret = 0;
2378
2379 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2380 if (!dpu_enc)
2381 return ERR_PTR(-ENOMEM);
2382
2383 ret = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2384 drm_enc_mode, NULL);
2385 if (ret) {
2386 devm_kfree(dev->dev, dpu_enc);
2387 return ERR_PTR(ret);
2388 }
2389
2390 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2391
2392 spin_lock_init(&dpu_enc->enc_spinlock);
2393 dpu_enc->enabled = false;
2394 mutex_init(&dpu_enc->enc_lock);
2395 mutex_init(&dpu_enc->rc_lock);
2396
2397 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2398 if (ret)
2399 goto fail;
2400
2401 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2402 timer_setup(&dpu_enc->frame_done_timer,
2403 dpu_encoder_frame_done_timeout, 0);
2404
2405 if (disp_info->intf_type == INTF_DP)
2406 dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
2407 priv->dp[disp_info->h_tile_instance[0]]);
2408
2409 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2410 dpu_encoder_off_work);
2411 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2412
2413 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2414
2415 DPU_DEBUG_ENC(dpu_enc, "created\n");
2416
2417 return &dpu_enc->base;
2418
2419 fail:
2420 DPU_ERROR("failed to create encoder\n");
2421 if (drm_enc)
2422 dpu_encoder_destroy(drm_enc);
2423
2424 return ERR_PTR(ret);
2425 }
2426
2427 /**
2428 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
2429 * @drm_enc: encoder pointer
2430 *
2431 * Wait for hardware to have flushed the current pending changes to hardware at
2432 * a vblank or CTL_START. Physical encoders will map this differently depending
2433 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
2434 *
2435 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2436 */
dpu_encoder_wait_for_commit_done(struct drm_encoder * drm_enc)2437 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
2438 {
2439 struct dpu_encoder_virt *dpu_enc = NULL;
2440 int i, ret = 0;
2441
2442 if (!drm_enc) {
2443 DPU_ERROR("invalid encoder\n");
2444 return -EINVAL;
2445 }
2446 dpu_enc = to_dpu_encoder_virt(drm_enc);
2447 DPU_DEBUG_ENC(dpu_enc, "\n");
2448
2449 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2450 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2451
2452 if (phys->ops.wait_for_commit_done) {
2453 DPU_ATRACE_BEGIN("wait_for_commit_done");
2454 ret = phys->ops.wait_for_commit_done(phys);
2455 DPU_ATRACE_END("wait_for_commit_done");
2456 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2457 dpu_enc->commit_done_timedout = true;
2458 msm_disp_snapshot_state(drm_enc->dev);
2459 }
2460 if (ret)
2461 return ret;
2462 }
2463 }
2464
2465 return ret;
2466 }
2467
2468 /**
2469 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
2470 * @drm_enc: encoder pointer
2471 *
2472 * Wait for the hardware to transfer all the pixels to the panel. Physical
2473 * encoders will map this differently depending on the type: vid mode -> vsync_irq,
2474 * cmd mode -> pp_done.
2475 *
2476 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2477 */
dpu_encoder_wait_for_tx_complete(struct drm_encoder * drm_enc)2478 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
2479 {
2480 struct dpu_encoder_virt *dpu_enc = NULL;
2481 int i, ret = 0;
2482
2483 if (!drm_enc) {
2484 DPU_ERROR("invalid encoder\n");
2485 return -EINVAL;
2486 }
2487 dpu_enc = to_dpu_encoder_virt(drm_enc);
2488 DPU_DEBUG_ENC(dpu_enc, "\n");
2489
2490 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2491 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2492
2493 if (phys->ops.wait_for_tx_complete) {
2494 DPU_ATRACE_BEGIN("wait_for_tx_complete");
2495 ret = phys->ops.wait_for_tx_complete(phys);
2496 DPU_ATRACE_END("wait_for_tx_complete");
2497 if (ret)
2498 return ret;
2499 }
2500 }
2501
2502 return ret;
2503 }
2504
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2505 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2506 {
2507 struct dpu_encoder_virt *dpu_enc = NULL;
2508
2509 if (!encoder) {
2510 DPU_ERROR("invalid encoder\n");
2511 return INTF_MODE_NONE;
2512 }
2513 dpu_enc = to_dpu_encoder_virt(encoder);
2514
2515 if (dpu_enc->cur_master)
2516 return dpu_enc->cur_master->intf_mode;
2517
2518 if (dpu_enc->num_phys_encs)
2519 return dpu_enc->phys_encs[0]->intf_mode;
2520
2521 return INTF_MODE_NONE;
2522 }
2523
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2524 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2525 {
2526 struct drm_encoder *encoder = phys_enc->parent;
2527 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2528
2529 return dpu_enc->dsc_mask;
2530 }
2531
dpu_encoder_phys_init(struct dpu_encoder_phys * phys_enc,struct dpu_enc_phys_init_params * p)2532 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
2533 struct dpu_enc_phys_init_params *p)
2534 {
2535 int i;
2536
2537 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
2538 phys_enc->hw_intf = p->hw_intf;
2539 phys_enc->hw_wb = p->hw_wb;
2540 phys_enc->parent = p->parent;
2541 phys_enc->dpu_kms = p->dpu_kms;
2542 phys_enc->split_role = p->split_role;
2543 phys_enc->enc_spinlock = p->enc_spinlock;
2544 phys_enc->enable_state = DPU_ENC_DISABLED;
2545
2546 for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++)
2547 phys_enc->irq[i] = -EINVAL;
2548
2549 atomic_set(&phys_enc->vblank_refcount, 0);
2550 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
2551 atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
2552
2553 atomic_set(&phys_enc->vsync_cnt, 0);
2554 atomic_set(&phys_enc->underrun_cnt, 0);
2555
2556 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
2557 }
2558