1 /*
2 * Copyright (C) ARM Ltd 2015
3 *
4 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 *
6 * SPDX-Licence-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <linux/bitops.h>
12 #include <pci_ids.h>
13 #include "pcie.h"
14
15 /* XpressRICH3 support */
16 #define XR3_CONFIG_BASE 0x7ff30000
17 #define XR3_RESET_BASE 0x7ff20000
18
19 #define XR3_PCI_ECAM_START 0x40000000
20 #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
21 #define XR3_PCI_IOSPACE_START 0x5f800000
22 #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
23 #define XR3_PCI_MEMSPACE_START 0x50000000
24 #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
25 #define XR3_PCI_MEMSPACE64_START 0x4000000000
26 #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
27
28 #define JUNO_V2M_MSI_START 0x2c1c0000
29 #define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */
30
31 #define XR3PCI_BASIC_STATUS 0x18
32 #define XR3PCI_BS_GEN_MASK (0xf << 8)
33 #define XR3PCI_BS_LINK_MASK 0xff
34
35 #define XR3PCI_VIRTCHAN_CREDITS 0x90
36 #define XR3PCI_BRIDGE_PCI_IDS 0x9c
37 #define XR3PCI_PEX_SPC2 0xd8
38
39 #define XR3PCI_ATR_PCIE_WIN0 0x600
40 #define XR3PCI_ATR_PCIE_WIN1 0x700
41 #define XR3PCI_ATR_AXI4_SLV0 0x800
42
43 #define XR3PCI_ATR_TABLE_SIZE 0x20
44 #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
45 #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
46 #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
47 #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
48 #define XR3PCI_ATR_TRSL_PARAM 0x10
49
50 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
51 #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004)
52 #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
53 #define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001)
54 #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
55 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
56
57 #define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
58 (PCI_SLOT(d) << 15) | \
59 (PCI_FUNC(d) << 12) | o)
60
61 #define JUNO_RESET_CTRL 0x1004
62 #define JUNO_RESET_CTRL_PHY BIT(0)
63 #define JUNO_RESET_CTRL_RC BIT(1)
64
65 #define JUNO_RESET_STATUS 0x1008
66 #define JUNO_RESET_STATUS_PLL BIT(0)
67 #define JUNO_RESET_STATUS_PHY BIT(1)
68 #define JUNO_RESET_STATUS_RC BIT(2)
69 #define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
70 JUNO_RESET_STATUS_PHY | \
71 JUNO_RESET_STATUS_RC)
72
xr3pci_set_atr_entry(unsigned long base,unsigned long src_addr,unsigned long trsl_addr,int window_size,int trsl_param)73 void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
74 unsigned long trsl_addr, int window_size,
75 int trsl_param)
76 {
77 /* X3PCI_ATR_SRC_ADDR_LOW:
78 - bit 0: enable entry,
79 - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
80 - bits 7-11: reserved
81 - bits 12-31: start of source address
82 */
83 writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
84 base + XR3PCI_ATR_SRC_ADDR_LOW);
85 writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
86 writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
87 writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
88 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
89
90 debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
91 src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
92 ((u64)1) << window_size, trsl_param);
93 }
94
xr3pci_setup_atr(void)95 void xr3pci_setup_atr(void)
96 {
97 /* setup PCIe to CPU address translation tables */
98 unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
99
100 /* forward all writes from PCIe to GIC V2M (used for MSI) */
101 xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
102 JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
103
104 base += XR3PCI_ATR_TABLE_SIZE;
105
106 /* PCIe devices can write anywhere in memory */
107 xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
108 31 /* grant access to all RAM under 4GB */,
109 XR3PCI_ATR_TRSLID_AXIMEMORY);
110 base += XR3PCI_ATR_TABLE_SIZE;
111 xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
112 XR3_PCI_MEMSPACE64_SIZE,
113 XR3PCI_ATR_TRSLID_AXIMEMORY);
114
115
116 /* setup CPU to PCIe address translation table */
117 base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
118
119 /* setup ECAM space to bus configuration interface */
120 xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
121 XR3PCI_ATR_TRSLID_PCIE_CONF);
122
123 base += XR3PCI_ATR_TABLE_SIZE;
124
125 /* setup IO space translation */
126 xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
127 XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
128
129 base += XR3PCI_ATR_TABLE_SIZE;
130
131 /* setup 32bit MEM space translation */
132 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
133 XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
134
135 base += XR3PCI_ATR_TABLE_SIZE;
136
137 /* setup 64bit MEM space translation */
138 xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
139 XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
140 }
141
xr3pci_init(void)142 void xr3pci_init(void)
143 {
144 u32 val;
145 int timeout = 200;
146
147 /* Initialise the XpressRICH3 PCIe host bridge */
148
149 /* add credits */
150 writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
151 writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
152 /* allow ECRC */
153 writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
154 /* setup the correct class code for the host bridge */
155 writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
156
157 /* reset phy and root complex */
158 writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
159 XR3_RESET_BASE + JUNO_RESET_CTRL);
160
161 do {
162 mdelay(1);
163 val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
164 } while (--timeout &&
165 (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
166
167 if (!timeout) {
168 printf("PCI XR3 Root complex reset timed out\n");
169 return;
170 }
171
172 /* Wait for the link to train */
173 mdelay(20);
174 timeout = 20;
175
176 do {
177 mdelay(1);
178 val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
179 } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
180
181 if (!(val & XR3PCI_BS_LINK_MASK)) {
182 printf("Failed to negotiate a link!\n");
183 return;
184 }
185
186 printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
187 val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
188
189 xr3pci_setup_atr();
190 }
191
vexpress64_pcie_init(void)192 void vexpress64_pcie_init(void)
193 {
194 xr3pci_init();
195 }
196