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Searched defs:XCHAL_RESET_VECTOR_VADDR (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/arch/xtensa/boot/boot-elf/
H A Dboot.lds.S18 .ResetVector.text XCHAL_RESET_VECTOR_VADDR : section
/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h302 #define XCHAL_RESET_VECTOR_VADDR 0xFE000020 macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h304 #define XCHAL_RESET_VECTOR_VADDR 0xFE000020 macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h320 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h342 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h341 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h340 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h400 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h376 #define XCHAL_RESET_VECTOR_VADDR 0x5FFE0000 macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h392 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h391 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h370 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h392 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h432 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h475 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h496 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h475 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h474 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h474 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h510 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h531 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h613 #define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR macro