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Searched defs:XCHAL_NUM_INSTRAM (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h167 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h171 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h170 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h207 #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h214 #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h217 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h196 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h284 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h262 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h288 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h306 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h391 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ macro