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Searched defs:XCHAL_ICACHE_LINESIZE (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h114 #define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h116 #define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h129 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h121 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h120 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h119 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h149 #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h156 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h160 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h159 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h138 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h180 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h180 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h209 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h208 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h208 #define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h208 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h186 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h217 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h231 #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h280 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ macro