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Searched defs:XCHAL_HAVE_TLBS (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h340 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h450 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h402 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h401 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h452 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h431 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h452 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h588 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h609 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h691 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro