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Searched defs:XCHAL_DCACHE_LINESIZE (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h115 #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h117 #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h130 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h157 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h150 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h121 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h122 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h120 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h160 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h139 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h161 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h181 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h181 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h209 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h209 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h209 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h187 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h210 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h218 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h232 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h281 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro