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Searched defs:VAL (Results 1 – 25 of 43) sorted by relevance

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/openbmc/qemu/tests/tcg/hexagon/
H A Dbrev.c59 #define BREV_STORE(SZ, PART, ADDR, VAL, INC) \ argument
67 #define BREV_STORE_b(ADDR, VAL, INC) \ argument
69 #define BREV_STORE_h(ADDR, VAL, INC) \ argument
71 #define BREV_STORE_f(ADDR, VAL, INC) \ argument
73 #define BREV_STORE_w(ADDR, VAL, INC) \ argument
75 #define BREV_STORE_d(ADDR, VAL, INC) \ argument
78 #define BREV_STORE_NEW(SZ, ADDR, VAL, INC) \ argument
89 #define BREV_STORE_bnew(ADDR, VAL, INC) \ argument
91 #define BREV_STORE_hnew(ADDR, VAL, INC) \ argument
93 #define BREV_STORE_wnew(ADDR, VAL, INC) \ argument
[all …]
H A Dcirc.c137 #define CIRC_STORE_IMM(SIZE, PART, VAL, ADDR, START, LEN, INC) \ argument
146 #define CIRC_STORE_IMM_b(VAL, ADDR, START, LEN, INC) \ argument
148 #define CIRC_STORE_IMM_h(VAL, ADDR, START, LEN, INC) \ argument
150 #define CIRC_STORE_IMM_f(VAL, ADDR, START, LEN, INC) \ argument
152 #define CIRC_STORE_IMM_w(VAL, ADDR, START, LEN, INC) \ argument
154 #define CIRC_STORE_IMM_d(VAL, ADDR, START, LEN, INC) \ argument
157 #define CIRC_STORE_NEW_IMM(SIZE, VAL, ADDR, START, LEN, INC) \ argument
169 #define CIRC_STORE_IMM_bnew(VAL, ADDR, START, LEN, INC) \ argument
171 #define CIRC_STORE_IMM_hnew(VAL, ADDR, START, LEN, INC) \ argument
173 #define CIRC_STORE_IMM_wnew(VAL, ADDR, START, LEN, INC) \ argument
[all …]
H A Dv69_hvx.c28 #define fVROUND(VAL, SHAMT) \ argument
31 #define fVSATUB(VAL) \ argument
36 #define fVSATUH(VAL) \ argument
/openbmc/qemu/target/hexagon/
H A Dmacros.h43 #define SET_USR_FIELD(FIELD, VAL) \ argument
217 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) argument
220 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) argument
222 #define fLSBOLD(VAL) ((VAL) & 1) argument
232 #define fLSBOLDNOT(VAL) \ argument
244 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) argument
249 #define fNEWREG(VAL) ((int32_t)(VAL)) argument
251 #define fNEWREG_ST(VAL) (VAL) argument
253 #define fVSATUVALN(N, VAL) \ argument
257 #define fSATUVALN(N, VAL) \ argument
[all …]
/openbmc/linux/arch/loongarch/kernel/
H A Dhw_breakpoint.c36 #define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \ argument
41 #define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \ argument
46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \ argument
56 #define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \ argument
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h48 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
59 #define fNOTQ(VAL) \ argument
94 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
100 #define fSETQBIT(REG, BITNO, VAL) fSETQBITS(REG, 1, 1, BITNO, VAL) argument
339 #define fVNOROUND(VAL, SHAMT) VAL argument
340 #define fVNOSAT(VAL) VAL argument
341 #define fVROUND(VAL, SHAMT) \ argument
350 #define fGET10BIT(COE, VAL, POS) \ argument
/openbmc/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c59 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
64 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
69 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
87 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ argument
/openbmc/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ argument
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ argument
/openbmc/linux/include/uapi/linux/
H A Dbtf.h92 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
93 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
94 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/openbmc/linux/tools/include/uapi/linux/
H A Dbtf.h92 #define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24) argument
93 #define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16) argument
94 #define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff) argument
/openbmc/linux/arch/arm/include/asm/
H A Dhw_breakpoint.h109 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
113 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
/openbmc/linux/arch/arm64/include/asm/
H A Dhw_breakpoint.h99 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
103 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
/openbmc/linux/arch/arm/kernel/
H A Dhw_breakpoint.c48 #define READ_WB_REG_CASE(OP2, M, VAL) \ argument
53 #define WRITE_WB_REG_CASE(OP2, M, VAL) \ argument
58 #define GEN_READ_WB_REG_CASES(OP2, VAL) \ argument
76 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ argument
/openbmc/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) argument
643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) argument
645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) argument
647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) argument
648 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) argument
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/openbmc/linux/drivers/net/ethernet/freescale/fs_enet/
H A Dmii-fec.c48 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
/openbmc/u-boot/include/
H A Dlcdvideo.h29 #define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) argument
/openbmc/linux/include/linux/
H A Ddma-mapping.h597 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) argument
599 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) argument
604 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) argument
606 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) argument
/openbmc/linux/drivers/scsi/
H A Dsun3x_esp.c50 #define dma_write32(VAL, REG) \ argument
H A Dmac_esp.c50 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
/openbmc/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h950 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) argument
951 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) argument
952 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) argument
953 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) argument
954 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) argument
955 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) argument
956 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) argument
991 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/openbmc/u-boot/drivers/net/
H A Dmcfmii.c33 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument
/openbmc/linux/drivers/hwmon/
H A Dsmsc47b397.c42 #define VAL 0x2f /* The value to read/write */ macro
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt39016.c70 #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 } argument
/openbmc/linux/drivers/watchdog/
H A Dit8712f_wdt.c57 #define VAL 0x2f /* The value to read/write */ macro
H A Dit87_wdt.c42 #define VAL 0x2f macro

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