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Searched defs:SSCR1_RIE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h43 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ macro
/openbmc/qemu/hw/arm/
H A Dstrongarm.c1391 #define SSCR1_RIE (1 << 0) macro
/openbmc/u-boot/include/
H A DSA-1100.h1063 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ macro