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Searched defs:PLLE_SS_CNTL_INTERP_RESET (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c653 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1124 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c938 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro