1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477, lan8804
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/ethtool_netlink.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/phy.h>
27 #include <linux/micrel_phy.h>
28 #include <linux/of.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/ptp_clock_kernel.h>
32 #include <linux/ptp_clock.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/net_tstamp.h>
35 #include <linux/gpio/consumer.h>
36
37 /* Operation Mode Strap Override */
38 #define MII_KSZPHY_OMSO 0x16
39 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
44
45 /* general Interrupt control/status reg in vendor specific block. */
46 #define MII_KSZPHY_INTCS 0x1B
47 #define KSZPHY_INTCS_JABBER BIT(15)
48 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50 #define KSZPHY_INTCS_PARELLEL BIT(12)
51 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
53 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54 #define KSZPHY_INTCS_LINK_UP BIT(8)
55 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
61
62 /* LinkMD Control/Status */
63 #define KSZ8081_LMD 0x1d
64 #define KSZ8081_LMD_ENABLE_TEST BIT(15)
65 #define KSZ8081_LMD_STAT_NORMAL 0
66 #define KSZ8081_LMD_STAT_OPEN 1
67 #define KSZ8081_LMD_STAT_SHORT 2
68 #define KSZ8081_LMD_STAT_FAIL 3
69 #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70 /* Short cable (<10 meter) has been detected by LinkMD */
71 #define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72 #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
73
74 #define KSZ9x31_LMD 0x12
75 #define KSZ9x31_LMD_VCT_EN BIT(15)
76 #define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77 #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78 #define KSZ9x31_LMD_VCT_SEL_RESULT 0
79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81 #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82 #define KSZ9x31_LMD_VCT_ST_NORMAL 0
83 #define KSZ9x31_LMD_VCT_ST_OPEN 1
84 #define KSZ9x31_LMD_VCT_ST_SHORT 2
85 #define KSZ9x31_LMD_VCT_ST_FAIL 3
86 #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89 #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93 #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
94
95 #define KSZPHY_WIRE_PAIR_MASK 0x3
96
97 #define LAN8814_CABLE_DIAG 0x12
98 #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99 #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100 #define LAN8814_PAIR_BIT_SHIFT 12
101
102 #define LAN8814_WIRE_PAIR_MASK 0xF
103
104 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105 #define LAN8814_INTC 0x18
106 #define LAN8814_INTS 0x1B
107
108 #define LAN8814_INT_LINK_DOWN BIT(2)
109 #define LAN8814_INT_LINK_UP BIT(0)
110 #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
112
113 #define LAN8814_INTR_CTRL_REG 0x34
114 #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
116
117 /* Represents 1ppm adjustment in 2^32 format with
118 * each nsec contains 4 clock cycles.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
120 */
121 #define LAN8814_1PPM_FORMAT 17179
122
123 #define PTP_RX_VERSION 0x0248
124 #define PTP_TX_VERSION 0x0288
125 #define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
126 #define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
127
128 #define PTP_RX_MOD 0x024F
129 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
130 #define PTP_RX_TIMESTAMP_EN 0x024D
131 #define PTP_TX_TIMESTAMP_EN 0x028D
132
133 #define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
134 #define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
135 #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
136 #define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
137
138 #define PTP_TX_PARSE_L2_ADDR_EN 0x0284
139 #define PTP_RX_PARSE_L2_ADDR_EN 0x0244
140
141 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285
142 #define PTP_RX_PARSE_IP_ADDR_EN 0x0245
143 #define LTC_HARD_RESET 0x023F
144 #define LTC_HARD_RESET_ BIT(0)
145
146 #define TSU_HARD_RESET 0x02C1
147 #define TSU_HARD_RESET_ BIT(0)
148
149 #define PTP_CMD_CTL 0x0200
150 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
151 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
152 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
153 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
154 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
155 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
156
157 #define PTP_CLOCK_SET_SEC_MID 0x0206
158 #define PTP_CLOCK_SET_SEC_LO 0x0207
159 #define PTP_CLOCK_SET_NS_HI 0x0208
160 #define PTP_CLOCK_SET_NS_LO 0x0209
161
162 #define PTP_CLOCK_READ_SEC_MID 0x022A
163 #define PTP_CLOCK_READ_SEC_LO 0x022B
164 #define PTP_CLOCK_READ_NS_HI 0x022C
165 #define PTP_CLOCK_READ_NS_LO 0x022D
166
167 #define PTP_OPERATING_MODE 0x0241
168 #define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
169
170 #define PTP_TX_MOD 0x028F
171 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
172 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
173
174 #define PTP_RX_PARSE_CONFIG 0x0242
175 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
176 #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
177 #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
178
179 #define PTP_TX_PARSE_CONFIG 0x0282
180 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
181 #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
182 #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
183
184 #define PTP_CLOCK_RATE_ADJ_HI 0x020C
185 #define PTP_CLOCK_RATE_ADJ_LO 0x020D
186 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
187
188 #define PTP_LTC_STEP_ADJ_HI 0x0212
189 #define PTP_LTC_STEP_ADJ_LO 0x0213
190 #define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
191
192 #define LAN8814_INTR_STS_REG 0x0033
193 #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
194 #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
195 #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
196 #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
197
198 #define PTP_CAP_INFO 0x022A
199 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
200 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
201
202 #define PTP_TX_EGRESS_SEC_HI 0x0296
203 #define PTP_TX_EGRESS_SEC_LO 0x0297
204 #define PTP_TX_EGRESS_NS_HI 0x0294
205 #define PTP_TX_EGRESS_NS_LO 0x0295
206 #define PTP_TX_MSG_HEADER2 0x0299
207
208 #define PTP_RX_INGRESS_SEC_HI 0x0256
209 #define PTP_RX_INGRESS_SEC_LO 0x0257
210 #define PTP_RX_INGRESS_NS_HI 0x0254
211 #define PTP_RX_INGRESS_NS_LO 0x0255
212 #define PTP_RX_MSG_HEADER2 0x0259
213
214 #define PTP_TSU_INT_EN 0x0200
215 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
216 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
217 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
218 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
219
220 #define PTP_TSU_INT_STS 0x0201
221 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
222 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
223 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
224 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
225
226 #define LAN8814_LED_CTRL_1 0x0
227 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
228
229 /* PHY Control 1 */
230 #define MII_KSZPHY_CTRL_1 0x1e
231 #define KSZ8081_CTRL1_MDIX_STAT BIT(4)
232
233 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
234 #define MII_KSZPHY_CTRL_2 0x1f
235 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
236 /* bitmap of PHY register to set interrupt mode */
237 #define KSZ8081_CTRL2_HP_MDIX BIT(15)
238 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
239 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
240 #define KSZ8081_CTRL2_FORCE_LINK BIT(11)
241 #define KSZ8081_CTRL2_POWER_SAVING BIT(10)
242 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
243 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
244
245 /* Write/read to/from extended registers */
246 #define MII_KSZPHY_EXTREG 0x0b
247 #define KSZPHY_EXTREG_WRITE 0x8000
248
249 #define MII_KSZPHY_EXTREG_WRITE 0x0c
250 #define MII_KSZPHY_EXTREG_READ 0x0d
251
252 /* Extended registers */
253 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
254 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
255 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
256
257 #define PS_TO_REG 200
258 #define FIFO_SIZE 8
259
260 /* Delay used to get the second part from the LTC */
261 #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
262
263 struct kszphy_hw_stat {
264 const char *string;
265 u8 reg;
266 u8 bits;
267 };
268
269 static struct kszphy_hw_stat kszphy_hw_stats[] = {
270 { "phy_receive_errors", 21, 16},
271 { "phy_idle_errors", 10, 8 },
272 };
273
274 struct kszphy_type {
275 u32 led_mode_reg;
276 u16 interrupt_level_mask;
277 u16 cable_diag_reg;
278 unsigned long pair_mask;
279 u16 disable_dll_tx_bit;
280 u16 disable_dll_rx_bit;
281 u16 disable_dll_mask;
282 bool has_broadcast_disable;
283 bool has_nand_tree_disable;
284 bool has_rmii_ref_clk_sel;
285 };
286
287 /* Shared structure between the PHYs of the same package. */
288 struct lan8814_shared_priv {
289 struct phy_device *phydev;
290 struct ptp_clock *ptp_clock;
291 struct ptp_clock_info ptp_clock_info;
292
293 /* Reference counter to how many ports in the package are enabling the
294 * timestamping
295 */
296 u8 ref;
297
298 /* Lock for ptp_clock and ref */
299 struct mutex shared_lock;
300 };
301
302 struct lan8814_ptp_rx_ts {
303 struct list_head list;
304 u32 seconds;
305 u32 nsec;
306 u16 seq_id;
307 };
308
309 struct kszphy_ptp_priv {
310 struct mii_timestamper mii_ts;
311 struct phy_device *phydev;
312
313 struct sk_buff_head tx_queue;
314 struct sk_buff_head rx_queue;
315
316 struct list_head rx_ts_list;
317 /* Lock for Rx ts fifo */
318 spinlock_t rx_ts_lock;
319
320 int hwts_tx_type;
321 enum hwtstamp_rx_filters rx_filter;
322 int layer;
323 int version;
324
325 struct ptp_clock *ptp_clock;
326 struct ptp_clock_info ptp_clock_info;
327 /* Lock for ptp_clock */
328 struct mutex ptp_lock;
329 struct ptp_pin_desc *pin_config;
330
331 s64 seconds;
332 /* Lock for accessing seconds */
333 spinlock_t seconds_lock;
334 };
335
336 struct kszphy_priv {
337 struct kszphy_ptp_priv ptp_priv;
338 const struct kszphy_type *type;
339 int led_mode;
340 u16 vct_ctrl1000;
341 bool rmii_ref_clk_sel;
342 bool rmii_ref_clk_sel_val;
343 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
344 };
345
346 static const struct kszphy_type lan8814_type = {
347 .led_mode_reg = ~LAN8814_LED_CTRL_1,
348 .cable_diag_reg = LAN8814_CABLE_DIAG,
349 .pair_mask = LAN8814_WIRE_PAIR_MASK,
350 };
351
352 static const struct kszphy_type ksz886x_type = {
353 .cable_diag_reg = KSZ8081_LMD,
354 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
355 };
356
357 static const struct kszphy_type ksz8021_type = {
358 .led_mode_reg = MII_KSZPHY_CTRL_2,
359 .has_broadcast_disable = true,
360 .has_nand_tree_disable = true,
361 .has_rmii_ref_clk_sel = true,
362 };
363
364 static const struct kszphy_type ksz8041_type = {
365 .led_mode_reg = MII_KSZPHY_CTRL_1,
366 };
367
368 static const struct kszphy_type ksz8051_type = {
369 .led_mode_reg = MII_KSZPHY_CTRL_2,
370 .has_nand_tree_disable = true,
371 };
372
373 static const struct kszphy_type ksz8081_type = {
374 .led_mode_reg = MII_KSZPHY_CTRL_2,
375 .has_broadcast_disable = true,
376 .has_nand_tree_disable = true,
377 .has_rmii_ref_clk_sel = true,
378 };
379
380 static const struct kszphy_type ks8737_type = {
381 .interrupt_level_mask = BIT(14),
382 };
383
384 static const struct kszphy_type ksz9021_type = {
385 .interrupt_level_mask = BIT(14),
386 };
387
388 static const struct kszphy_type ksz9131_type = {
389 .interrupt_level_mask = BIT(14),
390 .disable_dll_tx_bit = BIT(12),
391 .disable_dll_rx_bit = BIT(12),
392 .disable_dll_mask = BIT_MASK(12),
393 };
394
395 static const struct kszphy_type lan8841_type = {
396 .disable_dll_tx_bit = BIT(14),
397 .disable_dll_rx_bit = BIT(14),
398 .disable_dll_mask = BIT_MASK(14),
399 .cable_diag_reg = LAN8814_CABLE_DIAG,
400 .pair_mask = LAN8814_WIRE_PAIR_MASK,
401 };
402
kszphy_extended_write(struct phy_device * phydev,u32 regnum,u16 val)403 static int kszphy_extended_write(struct phy_device *phydev,
404 u32 regnum, u16 val)
405 {
406 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
407 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
408 }
409
kszphy_extended_read(struct phy_device * phydev,u32 regnum)410 static int kszphy_extended_read(struct phy_device *phydev,
411 u32 regnum)
412 {
413 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
414 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
415 }
416
kszphy_ack_interrupt(struct phy_device * phydev)417 static int kszphy_ack_interrupt(struct phy_device *phydev)
418 {
419 /* bit[7..0] int status, which is a read and clear register. */
420 int rc;
421
422 rc = phy_read(phydev, MII_KSZPHY_INTCS);
423
424 return (rc < 0) ? rc : 0;
425 }
426
kszphy_config_intr(struct phy_device * phydev)427 static int kszphy_config_intr(struct phy_device *phydev)
428 {
429 const struct kszphy_type *type = phydev->drv->driver_data;
430 int temp, err;
431 u16 mask;
432
433 if (type && type->interrupt_level_mask)
434 mask = type->interrupt_level_mask;
435 else
436 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
437
438 /* set the interrupt pin active low */
439 temp = phy_read(phydev, MII_KSZPHY_CTRL);
440 if (temp < 0)
441 return temp;
442 temp &= ~mask;
443 phy_write(phydev, MII_KSZPHY_CTRL, temp);
444
445 /* enable / disable interrupts */
446 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
447 err = kszphy_ack_interrupt(phydev);
448 if (err)
449 return err;
450
451 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
452 } else {
453 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
454 if (err)
455 return err;
456
457 err = kszphy_ack_interrupt(phydev);
458 }
459
460 return err;
461 }
462
kszphy_handle_interrupt(struct phy_device * phydev)463 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
464 {
465 int irq_status;
466
467 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
468 if (irq_status < 0) {
469 phy_error(phydev);
470 return IRQ_NONE;
471 }
472
473 if (!(irq_status & KSZPHY_INTCS_STATUS))
474 return IRQ_NONE;
475
476 phy_trigger_machine(phydev);
477
478 return IRQ_HANDLED;
479 }
480
kszphy_rmii_clk_sel(struct phy_device * phydev,bool val)481 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
482 {
483 int ctrl;
484
485 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
486 if (ctrl < 0)
487 return ctrl;
488
489 if (val)
490 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
491 else
492 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
493
494 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
495 }
496
kszphy_setup_led(struct phy_device * phydev,u32 reg,int val)497 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
498 {
499 int rc, temp, shift;
500
501 switch (reg) {
502 case MII_KSZPHY_CTRL_1:
503 shift = 14;
504 break;
505 case MII_KSZPHY_CTRL_2:
506 shift = 4;
507 break;
508 default:
509 return -EINVAL;
510 }
511
512 temp = phy_read(phydev, reg);
513 if (temp < 0) {
514 rc = temp;
515 goto out;
516 }
517
518 temp &= ~(3 << shift);
519 temp |= val << shift;
520 rc = phy_write(phydev, reg, temp);
521 out:
522 if (rc < 0)
523 phydev_err(phydev, "failed to set led mode\n");
524
525 return rc;
526 }
527
528 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
529 * unique (non-broadcast) address on a shared bus.
530 */
kszphy_broadcast_disable(struct phy_device * phydev)531 static int kszphy_broadcast_disable(struct phy_device *phydev)
532 {
533 int ret;
534
535 ret = phy_read(phydev, MII_KSZPHY_OMSO);
536 if (ret < 0)
537 goto out;
538
539 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
540 out:
541 if (ret)
542 phydev_err(phydev, "failed to disable broadcast address\n");
543
544 return ret;
545 }
546
kszphy_nand_tree_disable(struct phy_device * phydev)547 static int kszphy_nand_tree_disable(struct phy_device *phydev)
548 {
549 int ret;
550
551 ret = phy_read(phydev, MII_KSZPHY_OMSO);
552 if (ret < 0)
553 goto out;
554
555 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
556 return 0;
557
558 ret = phy_write(phydev, MII_KSZPHY_OMSO,
559 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
560 out:
561 if (ret)
562 phydev_err(phydev, "failed to disable NAND tree mode\n");
563
564 return ret;
565 }
566
567 /* Some config bits need to be set again on resume, handle them here. */
kszphy_config_reset(struct phy_device * phydev)568 static int kszphy_config_reset(struct phy_device *phydev)
569 {
570 struct kszphy_priv *priv = phydev->priv;
571 int ret;
572
573 if (priv->rmii_ref_clk_sel) {
574 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
575 if (ret) {
576 phydev_err(phydev,
577 "failed to set rmii reference clock\n");
578 return ret;
579 }
580 }
581
582 if (priv->type && priv->led_mode >= 0)
583 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
584
585 return 0;
586 }
587
kszphy_config_init(struct phy_device * phydev)588 static int kszphy_config_init(struct phy_device *phydev)
589 {
590 struct kszphy_priv *priv = phydev->priv;
591 const struct kszphy_type *type;
592
593 if (!priv)
594 return 0;
595
596 type = priv->type;
597
598 if (type && type->has_broadcast_disable)
599 kszphy_broadcast_disable(phydev);
600
601 if (type && type->has_nand_tree_disable)
602 kszphy_nand_tree_disable(phydev);
603
604 return kszphy_config_reset(phydev);
605 }
606
ksz8041_fiber_mode(struct phy_device * phydev)607 static int ksz8041_fiber_mode(struct phy_device *phydev)
608 {
609 struct device_node *of_node = phydev->mdio.dev.of_node;
610
611 return of_property_read_bool(of_node, "micrel,fiber-mode");
612 }
613
ksz8041_config_init(struct phy_device * phydev)614 static int ksz8041_config_init(struct phy_device *phydev)
615 {
616 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
617
618 /* Limit supported and advertised modes in fiber mode */
619 if (ksz8041_fiber_mode(phydev)) {
620 phydev->dev_flags |= MICREL_PHY_FXEN;
621 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
622 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
623
624 linkmode_and(phydev->supported, phydev->supported, mask);
625 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
626 phydev->supported);
627 linkmode_and(phydev->advertising, phydev->advertising, mask);
628 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
629 phydev->advertising);
630 phydev->autoneg = AUTONEG_DISABLE;
631 }
632
633 return kszphy_config_init(phydev);
634 }
635
ksz8041_config_aneg(struct phy_device * phydev)636 static int ksz8041_config_aneg(struct phy_device *phydev)
637 {
638 /* Skip auto-negotiation in fiber mode */
639 if (phydev->dev_flags & MICREL_PHY_FXEN) {
640 phydev->speed = SPEED_100;
641 return 0;
642 }
643
644 return genphy_config_aneg(phydev);
645 }
646
ksz8051_ksz8795_match_phy_device(struct phy_device * phydev,const bool ksz_8051)647 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
648 const bool ksz_8051)
649 {
650 int ret;
651
652 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
653 return 0;
654
655 ret = phy_read(phydev, MII_BMSR);
656 if (ret < 0)
657 return ret;
658
659 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
660 * exact PHY ID. However, they can be told apart by the extended
661 * capability registers presence. The KSZ8051 PHY has them while
662 * the switch does not.
663 */
664 ret &= BMSR_ERCAP;
665 if (ksz_8051)
666 return ret;
667 else
668 return !ret;
669 }
670
ksz8051_match_phy_device(struct phy_device * phydev)671 static int ksz8051_match_phy_device(struct phy_device *phydev)
672 {
673 return ksz8051_ksz8795_match_phy_device(phydev, true);
674 }
675
ksz8081_config_init(struct phy_device * phydev)676 static int ksz8081_config_init(struct phy_device *phydev)
677 {
678 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
679 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
680 * pull-down is missing, the factory test mode should be cleared by
681 * manually writing a 0.
682 */
683 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
684
685 return kszphy_config_init(phydev);
686 }
687
ksz8081_config_mdix(struct phy_device * phydev,u8 ctrl)688 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
689 {
690 u16 val;
691
692 switch (ctrl) {
693 case ETH_TP_MDI:
694 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
695 break;
696 case ETH_TP_MDI_X:
697 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
698 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
699 break;
700 case ETH_TP_MDI_AUTO:
701 val = 0;
702 break;
703 default:
704 return 0;
705 }
706
707 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
708 KSZ8081_CTRL2_HP_MDIX |
709 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
710 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
711 KSZ8081_CTRL2_HP_MDIX | val);
712 }
713
ksz8081_config_aneg(struct phy_device * phydev)714 static int ksz8081_config_aneg(struct phy_device *phydev)
715 {
716 int ret;
717
718 ret = genphy_config_aneg(phydev);
719 if (ret)
720 return ret;
721
722 /* The MDI-X configuration is automatically changed by the PHY after
723 * switching from autoneg off to on. So, take MDI-X configuration under
724 * own control and set it after autoneg configuration was done.
725 */
726 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
727 }
728
ksz8081_mdix_update(struct phy_device * phydev)729 static int ksz8081_mdix_update(struct phy_device *phydev)
730 {
731 int ret;
732
733 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
734 if (ret < 0)
735 return ret;
736
737 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
738 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
739 phydev->mdix_ctrl = ETH_TP_MDI_X;
740 else
741 phydev->mdix_ctrl = ETH_TP_MDI;
742 } else {
743 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
744 }
745
746 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
747 if (ret < 0)
748 return ret;
749
750 if (ret & KSZ8081_CTRL1_MDIX_STAT)
751 phydev->mdix = ETH_TP_MDI;
752 else
753 phydev->mdix = ETH_TP_MDI_X;
754
755 return 0;
756 }
757
ksz8081_read_status(struct phy_device * phydev)758 static int ksz8081_read_status(struct phy_device *phydev)
759 {
760 int ret;
761
762 ret = ksz8081_mdix_update(phydev);
763 if (ret < 0)
764 return ret;
765
766 return genphy_read_status(phydev);
767 }
768
ksz8061_config_init(struct phy_device * phydev)769 static int ksz8061_config_init(struct phy_device *phydev)
770 {
771 int ret;
772
773 /* Chip can be powered down by the bootstrap code. */
774 ret = phy_read(phydev, MII_BMCR);
775 if (ret < 0)
776 return ret;
777 if (ret & BMCR_PDOWN) {
778 ret = phy_write(phydev, MII_BMCR, ret & ~BMCR_PDOWN);
779 if (ret < 0)
780 return ret;
781 usleep_range(1000, 2000);
782 }
783
784 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
785 if (ret)
786 return ret;
787
788 return kszphy_config_init(phydev);
789 }
790
ksz8795_match_phy_device(struct phy_device * phydev)791 static int ksz8795_match_phy_device(struct phy_device *phydev)
792 {
793 return ksz8051_ksz8795_match_phy_device(phydev, false);
794 }
795
ksz9021_load_values_from_of(struct phy_device * phydev,const struct device_node * of_node,u16 reg,const char * field1,const char * field2,const char * field3,const char * field4)796 static int ksz9021_load_values_from_of(struct phy_device *phydev,
797 const struct device_node *of_node,
798 u16 reg,
799 const char *field1, const char *field2,
800 const char *field3, const char *field4)
801 {
802 int val1 = -1;
803 int val2 = -2;
804 int val3 = -3;
805 int val4 = -4;
806 int newval;
807 int matches = 0;
808
809 if (!of_property_read_u32(of_node, field1, &val1))
810 matches++;
811
812 if (!of_property_read_u32(of_node, field2, &val2))
813 matches++;
814
815 if (!of_property_read_u32(of_node, field3, &val3))
816 matches++;
817
818 if (!of_property_read_u32(of_node, field4, &val4))
819 matches++;
820
821 if (!matches)
822 return 0;
823
824 if (matches < 4)
825 newval = kszphy_extended_read(phydev, reg);
826 else
827 newval = 0;
828
829 if (val1 != -1)
830 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
831
832 if (val2 != -2)
833 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
834
835 if (val3 != -3)
836 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
837
838 if (val4 != -4)
839 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
840
841 return kszphy_extended_write(phydev, reg, newval);
842 }
843
ksz9021_config_init(struct phy_device * phydev)844 static int ksz9021_config_init(struct phy_device *phydev)
845 {
846 const struct device_node *of_node;
847 const struct device *dev_walker;
848
849 /* The Micrel driver has a deprecated option to place phy OF
850 * properties in the MAC node. Walk up the tree of devices to
851 * find a device with an OF node.
852 */
853 dev_walker = &phydev->mdio.dev;
854 do {
855 of_node = dev_walker->of_node;
856 dev_walker = dev_walker->parent;
857
858 } while (!of_node && dev_walker);
859
860 if (of_node) {
861 ksz9021_load_values_from_of(phydev, of_node,
862 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
863 "txen-skew-ps", "txc-skew-ps",
864 "rxdv-skew-ps", "rxc-skew-ps");
865 ksz9021_load_values_from_of(phydev, of_node,
866 MII_KSZPHY_RX_DATA_PAD_SKEW,
867 "rxd0-skew-ps", "rxd1-skew-ps",
868 "rxd2-skew-ps", "rxd3-skew-ps");
869 ksz9021_load_values_from_of(phydev, of_node,
870 MII_KSZPHY_TX_DATA_PAD_SKEW,
871 "txd0-skew-ps", "txd1-skew-ps",
872 "txd2-skew-ps", "txd3-skew-ps");
873 }
874 return 0;
875 }
876
877 #define KSZ9031_PS_TO_REG 60
878
879 /* Extended registers */
880 /* MMD Address 0x0 */
881 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
882 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
883
884 /* MMD Address 0x2 */
885 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
886 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
887 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
888
889 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
890 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
891 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
892 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
893 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
894
895 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
896 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
897 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
898 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
899 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
900
901 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
902 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
903 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
904
905 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
906 * provide different RGMII options we need to configure delay offset
907 * for each pad relative to build in delay.
908 */
909 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
910 * 1.80ns
911 */
912 #define RX_ID 0x7
913 #define RX_CLK_ID 0x19
914
915 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
916 * internal 1.2ns delay.
917 */
918 #define RX_ND 0xc
919 #define RX_CLK_ND 0x0
920
921 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
922 #define TX_ID 0x0
923 #define TX_CLK_ID 0x1f
924
925 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
926 * dealy
927 */
928 #define TX_ND 0x7
929 #define TX_CLK_ND 0xf
930
931 /* MMD Address 0x1C */
932 #define MII_KSZ9031RN_EDPD 0x23
933 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
934
ksz9031_of_load_skew_values(struct phy_device * phydev,const struct device_node * of_node,u16 reg,size_t field_sz,const char * field[],u8 numfields,bool * update)935 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
936 const struct device_node *of_node,
937 u16 reg, size_t field_sz,
938 const char *field[], u8 numfields,
939 bool *update)
940 {
941 int val[4] = {-1, -2, -3, -4};
942 int matches = 0;
943 u16 mask;
944 u16 maxval;
945 u16 newval;
946 int i;
947
948 for (i = 0; i < numfields; i++)
949 if (!of_property_read_u32(of_node, field[i], val + i))
950 matches++;
951
952 if (!matches)
953 return 0;
954
955 *update |= true;
956
957 if (matches < numfields)
958 newval = phy_read_mmd(phydev, 2, reg);
959 else
960 newval = 0;
961
962 maxval = (field_sz == 4) ? 0xf : 0x1f;
963 for (i = 0; i < numfields; i++)
964 if (val[i] != -(i + 1)) {
965 mask = 0xffff;
966 mask ^= maxval << (field_sz * i);
967 newval = (newval & mask) |
968 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
969 << (field_sz * i));
970 }
971
972 return phy_write_mmd(phydev, 2, reg, newval);
973 }
974
975 /* Center KSZ9031RNX FLP timing at 16ms. */
ksz9031_center_flp_timing(struct phy_device * phydev)976 static int ksz9031_center_flp_timing(struct phy_device *phydev)
977 {
978 int result;
979
980 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
981 0x0006);
982 if (result)
983 return result;
984
985 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
986 0x1A80);
987 if (result)
988 return result;
989
990 return genphy_restart_aneg(phydev);
991 }
992
993 /* Enable energy-detect power-down mode */
ksz9031_enable_edpd(struct phy_device * phydev)994 static int ksz9031_enable_edpd(struct phy_device *phydev)
995 {
996 int reg;
997
998 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
999 if (reg < 0)
1000 return reg;
1001 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
1002 reg | MII_KSZ9031RN_EDPD_ENABLE);
1003 }
1004
ksz9031_config_rgmii_delay(struct phy_device * phydev)1005 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1006 {
1007 u16 rx, tx, rx_clk, tx_clk;
1008 int ret;
1009
1010 switch (phydev->interface) {
1011 case PHY_INTERFACE_MODE_RGMII:
1012 tx = TX_ND;
1013 tx_clk = TX_CLK_ND;
1014 rx = RX_ND;
1015 rx_clk = RX_CLK_ND;
1016 break;
1017 case PHY_INTERFACE_MODE_RGMII_ID:
1018 tx = TX_ID;
1019 tx_clk = TX_CLK_ID;
1020 rx = RX_ID;
1021 rx_clk = RX_CLK_ID;
1022 break;
1023 case PHY_INTERFACE_MODE_RGMII_RXID:
1024 tx = TX_ND;
1025 tx_clk = TX_CLK_ND;
1026 rx = RX_ID;
1027 rx_clk = RX_CLK_ID;
1028 break;
1029 case PHY_INTERFACE_MODE_RGMII_TXID:
1030 tx = TX_ID;
1031 tx_clk = TX_CLK_ID;
1032 rx = RX_ND;
1033 rx_clk = RX_CLK_ND;
1034 break;
1035 default:
1036 return 0;
1037 }
1038
1039 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1040 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1041 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1042 if (ret < 0)
1043 return ret;
1044
1045 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1046 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1047 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1048 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1049 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1050 if (ret < 0)
1051 return ret;
1052
1053 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1054 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1055 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1056 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1057 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1058 if (ret < 0)
1059 return ret;
1060
1061 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1062 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1063 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1064 }
1065
ksz9031_config_init(struct phy_device * phydev)1066 static int ksz9031_config_init(struct phy_device *phydev)
1067 {
1068 const struct device_node *of_node;
1069 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1070 static const char *rx_data_skews[4] = {
1071 "rxd0-skew-ps", "rxd1-skew-ps",
1072 "rxd2-skew-ps", "rxd3-skew-ps"
1073 };
1074 static const char *tx_data_skews[4] = {
1075 "txd0-skew-ps", "txd1-skew-ps",
1076 "txd2-skew-ps", "txd3-skew-ps"
1077 };
1078 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1079 const struct device *dev_walker;
1080 int result;
1081
1082 result = ksz9031_enable_edpd(phydev);
1083 if (result < 0)
1084 return result;
1085
1086 /* The Micrel driver has a deprecated option to place phy OF
1087 * properties in the MAC node. Walk up the tree of devices to
1088 * find a device with an OF node.
1089 */
1090 dev_walker = &phydev->mdio.dev;
1091 do {
1092 of_node = dev_walker->of_node;
1093 dev_walker = dev_walker->parent;
1094 } while (!of_node && dev_walker);
1095
1096 if (of_node) {
1097 bool update = false;
1098
1099 if (phy_interface_is_rgmii(phydev)) {
1100 result = ksz9031_config_rgmii_delay(phydev);
1101 if (result < 0)
1102 return result;
1103 }
1104
1105 ksz9031_of_load_skew_values(phydev, of_node,
1106 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1107 clk_skews, 2, &update);
1108
1109 ksz9031_of_load_skew_values(phydev, of_node,
1110 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1111 control_skews, 2, &update);
1112
1113 ksz9031_of_load_skew_values(phydev, of_node,
1114 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1115 rx_data_skews, 4, &update);
1116
1117 ksz9031_of_load_skew_values(phydev, of_node,
1118 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1119 tx_data_skews, 4, &update);
1120
1121 if (update && !phy_interface_is_rgmii(phydev))
1122 phydev_warn(phydev,
1123 "*-skew-ps values should be used only with RGMII PHY modes\n");
1124
1125 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1126 * When the device links in the 1000BASE-T slave mode only,
1127 * the optional 125MHz reference output clock (CLK125_NDO)
1128 * has wide duty cycle variation.
1129 *
1130 * The optional CLK125_NDO clock does not meet the RGMII
1131 * 45/55 percent (min/max) duty cycle requirement and therefore
1132 * cannot be used directly by the MAC side for clocking
1133 * applications that have setup/hold time requirements on
1134 * rising and falling clock edges.
1135 *
1136 * Workaround:
1137 * Force the phy to be the master to receive a stable clock
1138 * which meets the duty cycle requirement.
1139 */
1140 if (of_property_read_bool(of_node, "micrel,force-master")) {
1141 result = phy_read(phydev, MII_CTRL1000);
1142 if (result < 0)
1143 goto err_force_master;
1144
1145 /* enable master mode, config & prefer master */
1146 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1147 result = phy_write(phydev, MII_CTRL1000, result);
1148 if (result < 0)
1149 goto err_force_master;
1150 }
1151 }
1152
1153 return ksz9031_center_flp_timing(phydev);
1154
1155 err_force_master:
1156 phydev_err(phydev, "failed to force the phy to master mode\n");
1157 return result;
1158 }
1159
1160 #define KSZ9131_SKEW_5BIT_MAX 2400
1161 #define KSZ9131_SKEW_4BIT_MAX 800
1162 #define KSZ9131_OFFSET 700
1163 #define KSZ9131_STEP 100
1164
ksz9131_of_load_skew_values(struct phy_device * phydev,struct device_node * of_node,u16 reg,size_t field_sz,char * field[],u8 numfields)1165 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1166 struct device_node *of_node,
1167 u16 reg, size_t field_sz,
1168 char *field[], u8 numfields)
1169 {
1170 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1171 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1172 int skewval, skewmax = 0;
1173 int matches = 0;
1174 u16 maxval;
1175 u16 newval;
1176 u16 mask;
1177 int i;
1178
1179 /* psec properties in dts should mean x pico seconds */
1180 if (field_sz == 5)
1181 skewmax = KSZ9131_SKEW_5BIT_MAX;
1182 else
1183 skewmax = KSZ9131_SKEW_4BIT_MAX;
1184
1185 for (i = 0; i < numfields; i++)
1186 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1187 if (skewval < -KSZ9131_OFFSET)
1188 skewval = -KSZ9131_OFFSET;
1189 else if (skewval > skewmax)
1190 skewval = skewmax;
1191
1192 val[i] = skewval + KSZ9131_OFFSET;
1193 matches++;
1194 }
1195
1196 if (!matches)
1197 return 0;
1198
1199 if (matches < numfields)
1200 newval = phy_read_mmd(phydev, 2, reg);
1201 else
1202 newval = 0;
1203
1204 maxval = (field_sz == 4) ? 0xf : 0x1f;
1205 for (i = 0; i < numfields; i++)
1206 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1207 mask = 0xffff;
1208 mask ^= maxval << (field_sz * i);
1209 newval = (newval & mask) |
1210 (((val[i] / KSZ9131_STEP) & maxval)
1211 << (field_sz * i));
1212 }
1213
1214 return phy_write_mmd(phydev, 2, reg, newval);
1215 }
1216
1217 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1218 #define KSZ9131RN_RXC_DLL_CTRL 76
1219 #define KSZ9131RN_TXC_DLL_CTRL 77
1220 #define KSZ9131RN_DLL_ENABLE_DELAY 0
1221
ksz9131_config_rgmii_delay(struct phy_device * phydev)1222 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1223 {
1224 const struct kszphy_type *type = phydev->drv->driver_data;
1225 u16 rxcdll_val, txcdll_val;
1226 int ret;
1227
1228 switch (phydev->interface) {
1229 case PHY_INTERFACE_MODE_RGMII:
1230 rxcdll_val = type->disable_dll_rx_bit;
1231 txcdll_val = type->disable_dll_tx_bit;
1232 break;
1233 case PHY_INTERFACE_MODE_RGMII_ID:
1234 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1235 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1236 break;
1237 case PHY_INTERFACE_MODE_RGMII_RXID:
1238 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1239 txcdll_val = type->disable_dll_tx_bit;
1240 break;
1241 case PHY_INTERFACE_MODE_RGMII_TXID:
1242 rxcdll_val = type->disable_dll_rx_bit;
1243 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1244 break;
1245 default:
1246 return 0;
1247 }
1248
1249 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1250 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1251 rxcdll_val);
1252 if (ret < 0)
1253 return ret;
1254
1255 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1256 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1257 txcdll_val);
1258 }
1259
1260 /* Silicon Errata DS80000693B
1261 *
1262 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1263 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1264 * according to the datasheet (off if there is no link).
1265 */
ksz9131_led_errata(struct phy_device * phydev)1266 static int ksz9131_led_errata(struct phy_device *phydev)
1267 {
1268 int reg;
1269
1270 reg = phy_read_mmd(phydev, 2, 0);
1271 if (reg < 0)
1272 return reg;
1273
1274 if (!(reg & BIT(4)))
1275 return 0;
1276
1277 return phy_set_bits(phydev, 0x1e, BIT(9));
1278 }
1279
ksz9131_config_init(struct phy_device * phydev)1280 static int ksz9131_config_init(struct phy_device *phydev)
1281 {
1282 struct device_node *of_node;
1283 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1284 char *rx_data_skews[4] = {
1285 "rxd0-skew-psec", "rxd1-skew-psec",
1286 "rxd2-skew-psec", "rxd3-skew-psec"
1287 };
1288 char *tx_data_skews[4] = {
1289 "txd0-skew-psec", "txd1-skew-psec",
1290 "txd2-skew-psec", "txd3-skew-psec"
1291 };
1292 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1293 const struct device *dev_walker;
1294 int ret;
1295
1296 dev_walker = &phydev->mdio.dev;
1297 do {
1298 of_node = dev_walker->of_node;
1299 dev_walker = dev_walker->parent;
1300 } while (!of_node && dev_walker);
1301
1302 if (!of_node)
1303 return 0;
1304
1305 if (phy_interface_is_rgmii(phydev)) {
1306 ret = ksz9131_config_rgmii_delay(phydev);
1307 if (ret < 0)
1308 return ret;
1309 }
1310
1311 ret = ksz9131_of_load_skew_values(phydev, of_node,
1312 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1313 clk_skews, 2);
1314 if (ret < 0)
1315 return ret;
1316
1317 ret = ksz9131_of_load_skew_values(phydev, of_node,
1318 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1319 control_skews, 2);
1320 if (ret < 0)
1321 return ret;
1322
1323 ret = ksz9131_of_load_skew_values(phydev, of_node,
1324 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1325 rx_data_skews, 4);
1326 if (ret < 0)
1327 return ret;
1328
1329 ret = ksz9131_of_load_skew_values(phydev, of_node,
1330 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1331 tx_data_skews, 4);
1332 if (ret < 0)
1333 return ret;
1334
1335 ret = ksz9131_led_errata(phydev);
1336 if (ret < 0)
1337 return ret;
1338
1339 return 0;
1340 }
1341
1342 #define MII_KSZ9131_AUTO_MDIX 0x1C
1343 #define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1344 #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1345
ksz9131_mdix_update(struct phy_device * phydev)1346 static int ksz9131_mdix_update(struct phy_device *phydev)
1347 {
1348 int ret;
1349
1350 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1351 if (ret < 0)
1352 return ret;
1353
1354 if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1355 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1356 phydev->mdix_ctrl = ETH_TP_MDI;
1357 else
1358 phydev->mdix_ctrl = ETH_TP_MDI_X;
1359 } else {
1360 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1361 }
1362
1363 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1364 phydev->mdix = ETH_TP_MDI;
1365 else
1366 phydev->mdix = ETH_TP_MDI_X;
1367
1368 return 0;
1369 }
1370
ksz9131_config_mdix(struct phy_device * phydev,u8 ctrl)1371 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1372 {
1373 u16 val;
1374
1375 switch (ctrl) {
1376 case ETH_TP_MDI:
1377 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1378 MII_KSZ9131_AUTO_MDI_SET;
1379 break;
1380 case ETH_TP_MDI_X:
1381 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1382 break;
1383 case ETH_TP_MDI_AUTO:
1384 val = 0;
1385 break;
1386 default:
1387 return 0;
1388 }
1389
1390 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1391 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1392 MII_KSZ9131_AUTO_MDI_SET, val);
1393 }
1394
ksz9131_read_status(struct phy_device * phydev)1395 static int ksz9131_read_status(struct phy_device *phydev)
1396 {
1397 int ret;
1398
1399 ret = ksz9131_mdix_update(phydev);
1400 if (ret < 0)
1401 return ret;
1402
1403 return genphy_read_status(phydev);
1404 }
1405
ksz9131_config_aneg(struct phy_device * phydev)1406 static int ksz9131_config_aneg(struct phy_device *phydev)
1407 {
1408 int ret;
1409
1410 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1411 if (ret)
1412 return ret;
1413
1414 return genphy_config_aneg(phydev);
1415 }
1416
ksz9477_get_features(struct phy_device * phydev)1417 static int ksz9477_get_features(struct phy_device *phydev)
1418 {
1419 int ret;
1420
1421 ret = genphy_read_abilities(phydev);
1422 if (ret)
1423 return ret;
1424
1425 /* The "EEE control and capability 1" (Register 3.20) seems to be
1426 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1427 * on the 7.60 will affect 3.20. So, we need to construct our own list
1428 * of caps.
1429 * KSZ8563R should have 100BaseTX/Full only.
1430 */
1431 linkmode_and(phydev->supported_eee, phydev->supported,
1432 PHY_EEE_CAP1_FEATURES);
1433
1434 return 0;
1435 }
1436
1437 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1438 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1439 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
ksz8873mll_read_status(struct phy_device * phydev)1440 static int ksz8873mll_read_status(struct phy_device *phydev)
1441 {
1442 int regval;
1443
1444 /* dummy read */
1445 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1446
1447 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1448
1449 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1450 phydev->duplex = DUPLEX_HALF;
1451 else
1452 phydev->duplex = DUPLEX_FULL;
1453
1454 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1455 phydev->speed = SPEED_10;
1456 else
1457 phydev->speed = SPEED_100;
1458
1459 phydev->link = 1;
1460 phydev->pause = phydev->asym_pause = 0;
1461
1462 return 0;
1463 }
1464
ksz9031_get_features(struct phy_device * phydev)1465 static int ksz9031_get_features(struct phy_device *phydev)
1466 {
1467 int ret;
1468
1469 ret = genphy_read_abilities(phydev);
1470 if (ret < 0)
1471 return ret;
1472
1473 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1474 * Whenever the device's Asymmetric Pause capability is set to 1,
1475 * link-up may fail after a link-up to link-down transition.
1476 *
1477 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1478 *
1479 * Workaround:
1480 * Do not enable the Asymmetric Pause capability bit.
1481 */
1482 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1483
1484 /* We force setting the Pause capability as the core will force the
1485 * Asymmetric Pause capability to 1 otherwise.
1486 */
1487 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1488
1489 return 0;
1490 }
1491
ksz9031_read_status(struct phy_device * phydev)1492 static int ksz9031_read_status(struct phy_device *phydev)
1493 {
1494 int err;
1495 int regval;
1496
1497 err = genphy_read_status(phydev);
1498 if (err)
1499 return err;
1500
1501 /* Make sure the PHY is not broken. Read idle error count,
1502 * and reset the PHY if it is maxed out.
1503 */
1504 regval = phy_read(phydev, MII_STAT1000);
1505 if ((regval & 0xFF) == 0xFF) {
1506 phy_init_hw(phydev);
1507 phydev->link = 0;
1508 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1509 phydev->drv->config_intr(phydev);
1510 return genphy_config_aneg(phydev);
1511 }
1512
1513 return 0;
1514 }
1515
ksz9x31_cable_test_start(struct phy_device * phydev)1516 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1517 {
1518 struct kszphy_priv *priv = phydev->priv;
1519 int ret;
1520
1521 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1522 * Prior to running the cable diagnostics, Auto-negotiation should
1523 * be disabled, full duplex set and the link speed set to 1000Mbps
1524 * via the Basic Control Register.
1525 */
1526 ret = phy_modify(phydev, MII_BMCR,
1527 BMCR_SPEED1000 | BMCR_FULLDPLX |
1528 BMCR_ANENABLE | BMCR_SPEED100,
1529 BMCR_SPEED1000 | BMCR_FULLDPLX);
1530 if (ret)
1531 return ret;
1532
1533 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1534 * The Master-Slave configuration should be set to Slave by writing
1535 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1536 * Register.
1537 */
1538 ret = phy_read(phydev, MII_CTRL1000);
1539 if (ret < 0)
1540 return ret;
1541
1542 /* Cache these bits, they need to be restored once LinkMD finishes. */
1543 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1544 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1545 ret |= CTL1000_ENABLE_MASTER;
1546
1547 return phy_write(phydev, MII_CTRL1000, ret);
1548 }
1549
ksz9x31_cable_test_result_trans(u16 status)1550 static int ksz9x31_cable_test_result_trans(u16 status)
1551 {
1552 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1553 case KSZ9x31_LMD_VCT_ST_NORMAL:
1554 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1555 case KSZ9x31_LMD_VCT_ST_OPEN:
1556 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1557 case KSZ9x31_LMD_VCT_ST_SHORT:
1558 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1559 case KSZ9x31_LMD_VCT_ST_FAIL:
1560 fallthrough;
1561 default:
1562 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1563 }
1564 }
1565
ksz9x31_cable_test_failed(u16 status)1566 static bool ksz9x31_cable_test_failed(u16 status)
1567 {
1568 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1569
1570 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1571 }
1572
ksz9x31_cable_test_fault_length_valid(u16 status)1573 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1574 {
1575 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1576 case KSZ9x31_LMD_VCT_ST_OPEN:
1577 fallthrough;
1578 case KSZ9x31_LMD_VCT_ST_SHORT:
1579 return true;
1580 }
1581 return false;
1582 }
1583
ksz9x31_cable_test_fault_length(struct phy_device * phydev,u16 stat)1584 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1585 {
1586 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1587
1588 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1589 *
1590 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1591 */
1592 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1593 dt = clamp(dt - 22, 0, 255);
1594
1595 return (dt * 400) / 10;
1596 }
1597
ksz9x31_cable_test_wait_for_completion(struct phy_device * phydev)1598 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1599 {
1600 int val, ret;
1601
1602 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1603 !(val & KSZ9x31_LMD_VCT_EN),
1604 30000, 100000, true);
1605
1606 return ret < 0 ? ret : 0;
1607 }
1608
ksz9x31_cable_test_get_pair(int pair)1609 static int ksz9x31_cable_test_get_pair(int pair)
1610 {
1611 static const int ethtool_pair[] = {
1612 ETHTOOL_A_CABLE_PAIR_A,
1613 ETHTOOL_A_CABLE_PAIR_B,
1614 ETHTOOL_A_CABLE_PAIR_C,
1615 ETHTOOL_A_CABLE_PAIR_D,
1616 };
1617
1618 return ethtool_pair[pair];
1619 }
1620
ksz9x31_cable_test_one_pair(struct phy_device * phydev,int pair)1621 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1622 {
1623 int ret, val;
1624
1625 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1626 * To test each individual cable pair, set the cable pair in the Cable
1627 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1628 * Diagnostic Register, along with setting the Cable Diagnostics Test
1629 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1630 * will self clear when the test is concluded.
1631 */
1632 ret = phy_write(phydev, KSZ9x31_LMD,
1633 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1634 if (ret)
1635 return ret;
1636
1637 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1638 if (ret)
1639 return ret;
1640
1641 val = phy_read(phydev, KSZ9x31_LMD);
1642 if (val < 0)
1643 return val;
1644
1645 if (ksz9x31_cable_test_failed(val))
1646 return -EAGAIN;
1647
1648 ret = ethnl_cable_test_result(phydev,
1649 ksz9x31_cable_test_get_pair(pair),
1650 ksz9x31_cable_test_result_trans(val));
1651 if (ret)
1652 return ret;
1653
1654 if (!ksz9x31_cable_test_fault_length_valid(val))
1655 return 0;
1656
1657 return ethnl_cable_test_fault_length(phydev,
1658 ksz9x31_cable_test_get_pair(pair),
1659 ksz9x31_cable_test_fault_length(phydev, val));
1660 }
1661
ksz9x31_cable_test_get_status(struct phy_device * phydev,bool * finished)1662 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1663 bool *finished)
1664 {
1665 struct kszphy_priv *priv = phydev->priv;
1666 unsigned long pair_mask = 0xf;
1667 int retries = 20;
1668 int pair, ret, rv;
1669
1670 *finished = false;
1671
1672 /* Try harder if link partner is active */
1673 while (pair_mask && retries--) {
1674 for_each_set_bit(pair, &pair_mask, 4) {
1675 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1676 if (ret == -EAGAIN)
1677 continue;
1678 if (ret < 0)
1679 return ret;
1680 clear_bit(pair, &pair_mask);
1681 }
1682 /* If link partner is in autonegotiation mode it will send 2ms
1683 * of FLPs with at least 6ms of silence.
1684 * Add 2ms sleep to have better chances to hit this silence.
1685 */
1686 if (pair_mask)
1687 usleep_range(2000, 3000);
1688 }
1689
1690 /* Report remaining unfinished pair result as unknown. */
1691 for_each_set_bit(pair, &pair_mask, 4) {
1692 ret = ethnl_cable_test_result(phydev,
1693 ksz9x31_cable_test_get_pair(pair),
1694 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1695 }
1696
1697 *finished = true;
1698
1699 /* Restore cached bits from before LinkMD got started. */
1700 rv = phy_modify(phydev, MII_CTRL1000,
1701 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1702 priv->vct_ctrl1000);
1703 if (rv)
1704 return rv;
1705
1706 return ret;
1707 }
1708
ksz8873mll_config_aneg(struct phy_device * phydev)1709 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1710 {
1711 return 0;
1712 }
1713
ksz886x_config_mdix(struct phy_device * phydev,u8 ctrl)1714 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1715 {
1716 u16 val;
1717
1718 switch (ctrl) {
1719 case ETH_TP_MDI:
1720 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1721 break;
1722 case ETH_TP_MDI_X:
1723 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1724 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1725 * sheet seems to be missing:
1726 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1727 * 0 = Normal operation (transmit on TX+/TX- pins)
1728 */
1729 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1730 break;
1731 case ETH_TP_MDI_AUTO:
1732 val = 0;
1733 break;
1734 default:
1735 return 0;
1736 }
1737
1738 return phy_modify(phydev, MII_BMCR,
1739 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1740 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1741 KSZ886X_BMCR_HP_MDIX | val);
1742 }
1743
ksz886x_config_aneg(struct phy_device * phydev)1744 static int ksz886x_config_aneg(struct phy_device *phydev)
1745 {
1746 int ret;
1747
1748 ret = genphy_config_aneg(phydev);
1749 if (ret)
1750 return ret;
1751
1752 /* The MDI-X configuration is automatically changed by the PHY after
1753 * switching from autoneg off to on. So, take MDI-X configuration under
1754 * own control and set it after autoneg configuration was done.
1755 */
1756 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1757 }
1758
ksz886x_mdix_update(struct phy_device * phydev)1759 static int ksz886x_mdix_update(struct phy_device *phydev)
1760 {
1761 int ret;
1762
1763 ret = phy_read(phydev, MII_BMCR);
1764 if (ret < 0)
1765 return ret;
1766
1767 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1768 if (ret & KSZ886X_BMCR_FORCE_MDI)
1769 phydev->mdix_ctrl = ETH_TP_MDI_X;
1770 else
1771 phydev->mdix_ctrl = ETH_TP_MDI;
1772 } else {
1773 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1774 }
1775
1776 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1777 if (ret < 0)
1778 return ret;
1779
1780 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1781 if (ret & KSZ886X_CTRL_MDIX_STAT)
1782 phydev->mdix = ETH_TP_MDI_X;
1783 else
1784 phydev->mdix = ETH_TP_MDI;
1785
1786 return 0;
1787 }
1788
ksz886x_read_status(struct phy_device * phydev)1789 static int ksz886x_read_status(struct phy_device *phydev)
1790 {
1791 int ret;
1792
1793 ret = ksz886x_mdix_update(phydev);
1794 if (ret < 0)
1795 return ret;
1796
1797 return genphy_read_status(phydev);
1798 }
1799
1800 struct ksz9477_errata_write {
1801 u8 dev_addr;
1802 u8 reg_addr;
1803 u16 val;
1804 };
1805
1806 static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1807 /* Register settings are needed to improve PHY receive performance */
1808 {0x01, 0x6f, 0xdd0b},
1809 {0x01, 0x8f, 0x6032},
1810 {0x01, 0x9d, 0x248c},
1811 {0x01, 0x75, 0x0060},
1812 {0x01, 0xd3, 0x7777},
1813 {0x1c, 0x06, 0x3008},
1814 {0x1c, 0x08, 0x2000},
1815
1816 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1817 {0x1c, 0x04, 0x00d0},
1818
1819 /* Register settings are required to meet data sheet supply current specifications */
1820 {0x1c, 0x13, 0x6eff},
1821 {0x1c, 0x14, 0xe6ff},
1822 {0x1c, 0x15, 0x6eff},
1823 {0x1c, 0x16, 0xe6ff},
1824 {0x1c, 0x17, 0x00ff},
1825 {0x1c, 0x18, 0x43ff},
1826 {0x1c, 0x19, 0xc3ff},
1827 {0x1c, 0x1a, 0x6fff},
1828 {0x1c, 0x1b, 0x07ff},
1829 {0x1c, 0x1c, 0x0fff},
1830 {0x1c, 0x1d, 0xe7ff},
1831 {0x1c, 0x1e, 0xefff},
1832 {0x1c, 0x20, 0xeeee},
1833 };
1834
ksz9477_phy_errata(struct phy_device * phydev)1835 static int ksz9477_phy_errata(struct phy_device *phydev)
1836 {
1837 int err;
1838 int i;
1839
1840 /* Apply PHY settings to address errata listed in
1841 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1842 * Silicon Errata and Data Sheet Clarification documents.
1843 *
1844 * Document notes: Before configuring the PHY MMD registers, it is
1845 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1846 * disabled by writing to register 0xN100-0xN101. After writing the
1847 * MMD registers, and after all errata workarounds that involve PHY
1848 * register settings, write register 0xN100-0xN101 again to enable
1849 * and restart auto-negotiation.
1850 */
1851 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1852 if (err)
1853 return err;
1854
1855 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1856 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1857
1858 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1859 if (err)
1860 return err;
1861 }
1862
1863 err = genphy_restart_aneg(phydev);
1864 if (err)
1865 return err;
1866
1867 return err;
1868 }
1869
ksz9477_config_init(struct phy_device * phydev)1870 static int ksz9477_config_init(struct phy_device *phydev)
1871 {
1872 int err;
1873
1874 /* Only KSZ9897 family of switches needs this fix. */
1875 if ((phydev->phy_id & 0xf) == 1) {
1876 err = ksz9477_phy_errata(phydev);
1877 if (err)
1878 return err;
1879 }
1880
1881 /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
1882 * in this switch shall be regarded as broken.
1883 */
1884 if (phydev->dev_flags & MICREL_NO_EEE)
1885 phydev->eee_broken_modes = -1;
1886
1887 return kszphy_config_init(phydev);
1888 }
1889
kszphy_get_sset_count(struct phy_device * phydev)1890 static int kszphy_get_sset_count(struct phy_device *phydev)
1891 {
1892 return ARRAY_SIZE(kszphy_hw_stats);
1893 }
1894
kszphy_get_strings(struct phy_device * phydev,u8 * data)1895 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1896 {
1897 int i;
1898
1899 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1900 strscpy(data + i * ETH_GSTRING_LEN,
1901 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1902 }
1903 }
1904
kszphy_get_stat(struct phy_device * phydev,int i)1905 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1906 {
1907 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1908 struct kszphy_priv *priv = phydev->priv;
1909 int val;
1910 u64 ret;
1911
1912 val = phy_read(phydev, stat.reg);
1913 if (val < 0) {
1914 ret = U64_MAX;
1915 } else {
1916 val = val & ((1 << stat.bits) - 1);
1917 priv->stats[i] += val;
1918 ret = priv->stats[i];
1919 }
1920
1921 return ret;
1922 }
1923
kszphy_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)1924 static void kszphy_get_stats(struct phy_device *phydev,
1925 struct ethtool_stats *stats, u64 *data)
1926 {
1927 int i;
1928
1929 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1930 data[i] = kszphy_get_stat(phydev, i);
1931 }
1932
kszphy_suspend(struct phy_device * phydev)1933 static int kszphy_suspend(struct phy_device *phydev)
1934 {
1935 /* Disable PHY Interrupts */
1936 if (phy_interrupt_is_valid(phydev)) {
1937 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1938 if (phydev->drv->config_intr)
1939 phydev->drv->config_intr(phydev);
1940 }
1941
1942 return genphy_suspend(phydev);
1943 }
1944
kszphy_parse_led_mode(struct phy_device * phydev)1945 static void kszphy_parse_led_mode(struct phy_device *phydev)
1946 {
1947 const struct kszphy_type *type = phydev->drv->driver_data;
1948 const struct device_node *np = phydev->mdio.dev.of_node;
1949 struct kszphy_priv *priv = phydev->priv;
1950 int ret;
1951
1952 if (type && type->led_mode_reg) {
1953 ret = of_property_read_u32(np, "micrel,led-mode",
1954 &priv->led_mode);
1955
1956 if (ret)
1957 priv->led_mode = -1;
1958
1959 if (priv->led_mode > 3) {
1960 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1961 priv->led_mode);
1962 priv->led_mode = -1;
1963 }
1964 } else {
1965 priv->led_mode = -1;
1966 }
1967 }
1968
kszphy_resume(struct phy_device * phydev)1969 static int kszphy_resume(struct phy_device *phydev)
1970 {
1971 int ret;
1972
1973 genphy_resume(phydev);
1974
1975 /* After switching from power-down to normal mode, an internal global
1976 * reset is automatically generated. Wait a minimum of 1 ms before
1977 * read/write access to the PHY registers.
1978 */
1979 usleep_range(1000, 2000);
1980
1981 ret = kszphy_config_reset(phydev);
1982 if (ret)
1983 return ret;
1984
1985 /* Enable PHY Interrupts */
1986 if (phy_interrupt_is_valid(phydev)) {
1987 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1988 if (phydev->drv->config_intr)
1989 phydev->drv->config_intr(phydev);
1990 }
1991
1992 return 0;
1993 }
1994
ksz9477_resume(struct phy_device * phydev)1995 static int ksz9477_resume(struct phy_device *phydev)
1996 {
1997 int ret;
1998
1999 /* No need to initialize registers if not powered down. */
2000 ret = phy_read(phydev, MII_BMCR);
2001 if (ret < 0)
2002 return ret;
2003 if (!(ret & BMCR_PDOWN))
2004 return 0;
2005
2006 genphy_resume(phydev);
2007
2008 /* After switching from power-down to normal mode, an internal global
2009 * reset is automatically generated. Wait a minimum of 1 ms before
2010 * read/write access to the PHY registers.
2011 */
2012 usleep_range(1000, 2000);
2013
2014 /* Only KSZ9897 family of switches needs this fix. */
2015 if ((phydev->phy_id & 0xf) == 1) {
2016 ret = ksz9477_phy_errata(phydev);
2017 if (ret)
2018 return ret;
2019 }
2020
2021 /* Enable PHY Interrupts */
2022 if (phy_interrupt_is_valid(phydev)) {
2023 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2024 if (phydev->drv->config_intr)
2025 phydev->drv->config_intr(phydev);
2026 }
2027
2028 return 0;
2029 }
2030
ksz8061_resume(struct phy_device * phydev)2031 static int ksz8061_resume(struct phy_device *phydev)
2032 {
2033 int ret;
2034
2035 /* This function can be called twice when the Ethernet device is on. */
2036 ret = phy_read(phydev, MII_BMCR);
2037 if (ret < 0)
2038 return ret;
2039 if (!(ret & BMCR_PDOWN))
2040 return 0;
2041
2042 genphy_resume(phydev);
2043 usleep_range(1000, 2000);
2044
2045 /* Re-program the value after chip is reset. */
2046 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
2047 if (ret)
2048 return ret;
2049
2050 /* Enable PHY Interrupts */
2051 if (phy_interrupt_is_valid(phydev)) {
2052 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2053 if (phydev->drv->config_intr)
2054 phydev->drv->config_intr(phydev);
2055 }
2056
2057 return 0;
2058 }
2059
kszphy_probe(struct phy_device * phydev)2060 static int kszphy_probe(struct phy_device *phydev)
2061 {
2062 const struct kszphy_type *type = phydev->drv->driver_data;
2063 const struct device_node *np = phydev->mdio.dev.of_node;
2064 struct kszphy_priv *priv;
2065 struct clk *clk;
2066
2067 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2068 if (!priv)
2069 return -ENOMEM;
2070
2071 phydev->priv = priv;
2072
2073 priv->type = type;
2074
2075 kszphy_parse_led_mode(phydev);
2076
2077 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
2078 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2079 if (!IS_ERR_OR_NULL(clk)) {
2080 unsigned long rate = clk_get_rate(clk);
2081 bool rmii_ref_clk_sel_25_mhz;
2082
2083 if (type)
2084 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2085 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2086 "micrel,rmii-reference-clock-select-25-mhz");
2087
2088 if (rate > 24500000 && rate < 25500000) {
2089 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2090 } else if (rate > 49500000 && rate < 50500000) {
2091 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2092 } else {
2093 phydev_err(phydev, "Clock rate out of range: %ld\n",
2094 rate);
2095 return -EINVAL;
2096 }
2097 }
2098
2099 if (ksz8041_fiber_mode(phydev))
2100 phydev->port = PORT_FIBRE;
2101
2102 /* Support legacy board-file configuration */
2103 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2104 priv->rmii_ref_clk_sel = true;
2105 priv->rmii_ref_clk_sel_val = true;
2106 }
2107
2108 return 0;
2109 }
2110
lan8814_cable_test_start(struct phy_device * phydev)2111 static int lan8814_cable_test_start(struct phy_device *phydev)
2112 {
2113 /* If autoneg is enabled, we won't be able to test cross pair
2114 * short. In this case, the PHY will "detect" a link and
2115 * confuse the internal state machine - disable auto neg here.
2116 * Set the speed to 1000mbit and full duplex.
2117 */
2118 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2119 BMCR_SPEED1000 | BMCR_FULLDPLX);
2120 }
2121
ksz886x_cable_test_start(struct phy_device * phydev)2122 static int ksz886x_cable_test_start(struct phy_device *phydev)
2123 {
2124 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2125 return -EOPNOTSUPP;
2126
2127 /* If autoneg is enabled, we won't be able to test cross pair
2128 * short. In this case, the PHY will "detect" a link and
2129 * confuse the internal state machine - disable auto neg here.
2130 * If autoneg is disabled, we should set the speed to 10mbit.
2131 */
2132 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2133 }
2134
ksz886x_cable_test_result_trans(u16 status,u16 mask)2135 static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2136 {
2137 switch (FIELD_GET(mask, status)) {
2138 case KSZ8081_LMD_STAT_NORMAL:
2139 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2140 case KSZ8081_LMD_STAT_SHORT:
2141 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2142 case KSZ8081_LMD_STAT_OPEN:
2143 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2144 case KSZ8081_LMD_STAT_FAIL:
2145 fallthrough;
2146 default:
2147 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2148 }
2149 }
2150
ksz886x_cable_test_failed(u16 status,u16 mask)2151 static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2152 {
2153 return FIELD_GET(mask, status) ==
2154 KSZ8081_LMD_STAT_FAIL;
2155 }
2156
ksz886x_cable_test_fault_length_valid(u16 status,u16 mask)2157 static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2158 {
2159 switch (FIELD_GET(mask, status)) {
2160 case KSZ8081_LMD_STAT_OPEN:
2161 fallthrough;
2162 case KSZ8081_LMD_STAT_SHORT:
2163 return true;
2164 }
2165 return false;
2166 }
2167
ksz886x_cable_test_fault_length(struct phy_device * phydev,u16 status,u16 data_mask)2168 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2169 u16 status, u16 data_mask)
2170 {
2171 int dt;
2172
2173 /* According to the data sheet the distance to the fault is
2174 * DELTA_TIME * 0.4 meters for ksz phys.
2175 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2176 */
2177 dt = FIELD_GET(data_mask, status);
2178
2179 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2180 return ((dt - 22) * 800) / 10;
2181 else
2182 return (dt * 400) / 10;
2183 }
2184
ksz886x_cable_test_wait_for_completion(struct phy_device * phydev)2185 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2186 {
2187 const struct kszphy_type *type = phydev->drv->driver_data;
2188 int val, ret;
2189
2190 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2191 !(val & KSZ8081_LMD_ENABLE_TEST),
2192 30000, 100000, true);
2193
2194 return ret < 0 ? ret : 0;
2195 }
2196
lan8814_cable_test_one_pair(struct phy_device * phydev,int pair)2197 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2198 {
2199 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2200 ETHTOOL_A_CABLE_PAIR_B,
2201 ETHTOOL_A_CABLE_PAIR_C,
2202 ETHTOOL_A_CABLE_PAIR_D,
2203 };
2204 u32 fault_length;
2205 int ret;
2206 int val;
2207
2208 val = KSZ8081_LMD_ENABLE_TEST;
2209 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2210
2211 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2212 if (ret < 0)
2213 return ret;
2214
2215 ret = ksz886x_cable_test_wait_for_completion(phydev);
2216 if (ret)
2217 return ret;
2218
2219 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2220 if (val < 0)
2221 return val;
2222
2223 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2224 return -EAGAIN;
2225
2226 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2227 ksz886x_cable_test_result_trans(val,
2228 LAN8814_CABLE_DIAG_STAT_MASK
2229 ));
2230 if (ret)
2231 return ret;
2232
2233 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2234 return 0;
2235
2236 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2237 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2238
2239 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2240 }
2241
ksz886x_cable_test_one_pair(struct phy_device * phydev,int pair)2242 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2243 {
2244 static const int ethtool_pair[] = {
2245 ETHTOOL_A_CABLE_PAIR_A,
2246 ETHTOOL_A_CABLE_PAIR_B,
2247 };
2248 int ret, val, mdix;
2249 u32 fault_length;
2250
2251 /* There is no way to choice the pair, like we do one ksz9031.
2252 * We can workaround this limitation by using the MDI-X functionality.
2253 */
2254 if (pair == 0)
2255 mdix = ETH_TP_MDI;
2256 else
2257 mdix = ETH_TP_MDI_X;
2258
2259 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2260 case PHY_ID_KSZ8081:
2261 ret = ksz8081_config_mdix(phydev, mdix);
2262 break;
2263 case PHY_ID_KSZ886X:
2264 ret = ksz886x_config_mdix(phydev, mdix);
2265 break;
2266 default:
2267 ret = -ENODEV;
2268 }
2269
2270 if (ret)
2271 return ret;
2272
2273 /* Now we are ready to fire. This command will send a 100ns pulse
2274 * to the pair.
2275 */
2276 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2277 if (ret)
2278 return ret;
2279
2280 ret = ksz886x_cable_test_wait_for_completion(phydev);
2281 if (ret)
2282 return ret;
2283
2284 val = phy_read(phydev, KSZ8081_LMD);
2285 if (val < 0)
2286 return val;
2287
2288 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2289 return -EAGAIN;
2290
2291 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2292 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2293 if (ret)
2294 return ret;
2295
2296 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2297 return 0;
2298
2299 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2300
2301 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2302 }
2303
ksz886x_cable_test_get_status(struct phy_device * phydev,bool * finished)2304 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2305 bool *finished)
2306 {
2307 const struct kszphy_type *type = phydev->drv->driver_data;
2308 unsigned long pair_mask = type->pair_mask;
2309 int retries = 20;
2310 int ret = 0;
2311 int pair;
2312
2313 *finished = false;
2314
2315 /* Try harder if link partner is active */
2316 while (pair_mask && retries--) {
2317 for_each_set_bit(pair, &pair_mask, 4) {
2318 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2319 ret = lan8814_cable_test_one_pair(phydev, pair);
2320 else
2321 ret = ksz886x_cable_test_one_pair(phydev, pair);
2322 if (ret == -EAGAIN)
2323 continue;
2324 if (ret < 0)
2325 return ret;
2326 clear_bit(pair, &pair_mask);
2327 }
2328 /* If link partner is in autonegotiation mode it will send 2ms
2329 * of FLPs with at least 6ms of silence.
2330 * Add 2ms sleep to have better chances to hit this silence.
2331 */
2332 if (pair_mask)
2333 msleep(2);
2334 }
2335
2336 *finished = true;
2337
2338 return ret;
2339 }
2340
2341 #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2342 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2343 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2344
2345 #define LAN8814_QSGMII_SOFT_RESET 0x43
2346 #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2347 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2348 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2349 #define LAN8814_ALIGN_SWAP 0x4a
2350 #define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2351 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2352
2353 #define LAN8804_ALIGN_SWAP 0x4a
2354 #define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2355 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2356 #define LAN8814_CLOCK_MANAGEMENT 0xd
2357 #define LAN8814_LINK_QUALITY 0x8e
2358
lanphy_read_page_reg(struct phy_device * phydev,int page,u32 addr)2359 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2360 {
2361 int data;
2362
2363 phy_lock_mdio_bus(phydev);
2364 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2365 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2366 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2367 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2368 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2369 phy_unlock_mdio_bus(phydev);
2370
2371 return data;
2372 }
2373
lanphy_write_page_reg(struct phy_device * phydev,int page,u16 addr,u16 val)2374 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2375 u16 val)
2376 {
2377 phy_lock_mdio_bus(phydev);
2378 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2379 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2380 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2381 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2382
2383 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2384 if (val != 0)
2385 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2386 val);
2387 phy_unlock_mdio_bus(phydev);
2388 return val;
2389 }
2390
lan8814_config_ts_intr(struct phy_device * phydev,bool enable)2391 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2392 {
2393 u16 val = 0;
2394
2395 if (enable)
2396 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2397 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2398 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2399 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2400
2401 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2402 }
2403
lan8814_ptp_rx_ts_get(struct phy_device * phydev,u32 * seconds,u32 * nano_seconds,u16 * seq_id)2404 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2405 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2406 {
2407 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2408 *seconds = (*seconds << 16) |
2409 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2410
2411 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2412 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2413 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2414
2415 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2416 }
2417
lan8814_ptp_tx_ts_get(struct phy_device * phydev,u32 * seconds,u32 * nano_seconds,u16 * seq_id)2418 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2419 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2420 {
2421 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2422 *seconds = *seconds << 16 |
2423 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2424
2425 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2426 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2427 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2428
2429 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2430 }
2431
lan8814_ts_info(struct mii_timestamper * mii_ts,struct ethtool_ts_info * info)2432 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2433 {
2434 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2435 struct phy_device *phydev = ptp_priv->phydev;
2436 struct lan8814_shared_priv *shared = phydev->shared->priv;
2437
2438 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2439 SOF_TIMESTAMPING_RX_HARDWARE |
2440 SOF_TIMESTAMPING_RAW_HARDWARE;
2441
2442 info->phc_index = ptp_clock_index(shared->ptp_clock);
2443
2444 info->tx_types =
2445 (1 << HWTSTAMP_TX_OFF) |
2446 (1 << HWTSTAMP_TX_ON) |
2447 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2448
2449 info->rx_filters =
2450 (1 << HWTSTAMP_FILTER_NONE) |
2451 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2452 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2453 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2454 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2455
2456 return 0;
2457 }
2458
lan8814_flush_fifo(struct phy_device * phydev,bool egress)2459 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2460 {
2461 int i;
2462
2463 for (i = 0; i < FIFO_SIZE; ++i)
2464 lanphy_read_page_reg(phydev, 5,
2465 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2466
2467 /* Read to clear overflow status bit */
2468 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2469 }
2470
lan8814_hwtstamp(struct mii_timestamper * mii_ts,struct ifreq * ifr)2471 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2472 {
2473 struct kszphy_ptp_priv *ptp_priv =
2474 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2475 struct phy_device *phydev = ptp_priv->phydev;
2476 struct lan8814_shared_priv *shared = phydev->shared->priv;
2477 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2478 struct hwtstamp_config config;
2479 int txcfg = 0, rxcfg = 0;
2480 int pkt_ts_enable;
2481 int tx_mod;
2482
2483 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2484 return -EFAULT;
2485
2486 ptp_priv->hwts_tx_type = config.tx_type;
2487 ptp_priv->rx_filter = config.rx_filter;
2488
2489 switch (config.rx_filter) {
2490 case HWTSTAMP_FILTER_NONE:
2491 ptp_priv->layer = 0;
2492 ptp_priv->version = 0;
2493 break;
2494 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2495 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2496 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2497 ptp_priv->layer = PTP_CLASS_L4;
2498 ptp_priv->version = PTP_CLASS_V2;
2499 break;
2500 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2501 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2502 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2503 ptp_priv->layer = PTP_CLASS_L2;
2504 ptp_priv->version = PTP_CLASS_V2;
2505 break;
2506 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2507 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2508 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2509 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2510 ptp_priv->version = PTP_CLASS_V2;
2511 break;
2512 default:
2513 return -ERANGE;
2514 }
2515
2516 if (ptp_priv->layer & PTP_CLASS_L2) {
2517 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2518 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2519 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2520 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2521 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2522 }
2523 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2524 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2525
2526 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2527 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2528 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2529 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2530
2531 tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2532 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2533 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2534 tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2535 } else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2536 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2537 tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2538 }
2539
2540 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2541 lan8814_config_ts_intr(ptp_priv->phydev, true);
2542 else
2543 lan8814_config_ts_intr(ptp_priv->phydev, false);
2544
2545 mutex_lock(&shared->shared_lock);
2546 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2547 shared->ref++;
2548 else
2549 shared->ref--;
2550
2551 if (shared->ref)
2552 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2553 PTP_CMD_CTL_PTP_ENABLE_);
2554 else
2555 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2556 PTP_CMD_CTL_PTP_DISABLE_);
2557 mutex_unlock(&shared->shared_lock);
2558
2559 /* In case of multiple starts and stops, these needs to be cleared */
2560 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2561 list_del(&rx_ts->list);
2562 kfree(rx_ts);
2563 }
2564 skb_queue_purge(&ptp_priv->rx_queue);
2565 skb_queue_purge(&ptp_priv->tx_queue);
2566
2567 lan8814_flush_fifo(ptp_priv->phydev, false);
2568 lan8814_flush_fifo(ptp_priv->phydev, true);
2569
2570 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2571 }
2572
lan8814_txtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)2573 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2574 struct sk_buff *skb, int type)
2575 {
2576 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2577
2578 switch (ptp_priv->hwts_tx_type) {
2579 case HWTSTAMP_TX_ONESTEP_SYNC:
2580 if (ptp_msg_is_sync(skb, type)) {
2581 kfree_skb(skb);
2582 return;
2583 }
2584 fallthrough;
2585 case HWTSTAMP_TX_ON:
2586 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2587 skb_queue_tail(&ptp_priv->tx_queue, skb);
2588 break;
2589 case HWTSTAMP_TX_OFF:
2590 default:
2591 kfree_skb(skb);
2592 break;
2593 }
2594 }
2595
lan8814_get_sig_rx(struct sk_buff * skb,u16 * sig)2596 static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2597 {
2598 struct ptp_header *ptp_header;
2599 u32 type;
2600
2601 skb_push(skb, ETH_HLEN);
2602 type = ptp_classify_raw(skb);
2603 ptp_header = ptp_parse_header(skb, type);
2604 skb_pull_inline(skb, ETH_HLEN);
2605
2606 if (!ptp_header)
2607 return false;
2608
2609 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2610 return true;
2611 }
2612
lan8814_match_rx_skb(struct kszphy_ptp_priv * ptp_priv,struct sk_buff * skb)2613 static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2614 struct sk_buff *skb)
2615 {
2616 struct skb_shared_hwtstamps *shhwtstamps;
2617 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2618 unsigned long flags;
2619 bool ret = false;
2620 u16 skb_sig;
2621
2622 if (!lan8814_get_sig_rx(skb, &skb_sig))
2623 return ret;
2624
2625 /* Iterate over all RX timestamps and match it with the received skbs */
2626 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2627 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2628 /* Check if we found the signature we were looking for. */
2629 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2630 continue;
2631
2632 shhwtstamps = skb_hwtstamps(skb);
2633 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2634 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2635 rx_ts->nsec);
2636 list_del(&rx_ts->list);
2637 kfree(rx_ts);
2638
2639 ret = true;
2640 break;
2641 }
2642 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2643
2644 if (ret)
2645 netif_rx(skb);
2646 return ret;
2647 }
2648
lan8814_rxtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)2649 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2650 {
2651 struct kszphy_ptp_priv *ptp_priv =
2652 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2653
2654 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2655 type == PTP_CLASS_NONE)
2656 return false;
2657
2658 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2659 return false;
2660
2661 /* If we failed to match then add it to the queue for when the timestamp
2662 * will come
2663 */
2664 if (!lan8814_match_rx_skb(ptp_priv, skb))
2665 skb_queue_tail(&ptp_priv->rx_queue, skb);
2666
2667 return true;
2668 }
2669
lan8814_ptp_clock_set(struct phy_device * phydev,u32 seconds,u32 nano_seconds)2670 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2671 u32 seconds, u32 nano_seconds)
2672 {
2673 u32 sec_low, sec_high, nsec_low, nsec_high;
2674
2675 sec_low = seconds & 0xffff;
2676 sec_high = (seconds >> 16) & 0xffff;
2677 nsec_low = nano_seconds & 0xffff;
2678 nsec_high = (nano_seconds >> 16) & 0x3fff;
2679
2680 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2681 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2682 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2683 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2684
2685 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2686 }
2687
lan8814_ptp_clock_get(struct phy_device * phydev,u32 * seconds,u32 * nano_seconds)2688 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2689 u32 *seconds, u32 *nano_seconds)
2690 {
2691 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2692
2693 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2694 *seconds = (*seconds << 16) |
2695 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2696
2697 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2698 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2699 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2700 }
2701
lan8814_ptpci_gettime64(struct ptp_clock_info * ptpci,struct timespec64 * ts)2702 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2703 struct timespec64 *ts)
2704 {
2705 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2706 ptp_clock_info);
2707 struct phy_device *phydev = shared->phydev;
2708 u32 nano_seconds;
2709 u32 seconds;
2710
2711 mutex_lock(&shared->shared_lock);
2712 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2713 mutex_unlock(&shared->shared_lock);
2714 ts->tv_sec = seconds;
2715 ts->tv_nsec = nano_seconds;
2716
2717 return 0;
2718 }
2719
lan8814_ptpci_settime64(struct ptp_clock_info * ptpci,const struct timespec64 * ts)2720 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2721 const struct timespec64 *ts)
2722 {
2723 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2724 ptp_clock_info);
2725 struct phy_device *phydev = shared->phydev;
2726
2727 mutex_lock(&shared->shared_lock);
2728 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2729 mutex_unlock(&shared->shared_lock);
2730
2731 return 0;
2732 }
2733
lan8814_ptp_clock_step(struct phy_device * phydev,s64 time_step_ns)2734 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2735 s64 time_step_ns)
2736 {
2737 u32 nano_seconds_step;
2738 u64 abs_time_step_ns;
2739 u32 unsigned_seconds;
2740 u32 nano_seconds;
2741 u32 remainder;
2742 s32 seconds;
2743
2744 if (time_step_ns > 15000000000LL) {
2745 /* convert to clock set */
2746 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2747 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2748 &remainder);
2749 nano_seconds += remainder;
2750 if (nano_seconds >= 1000000000) {
2751 unsigned_seconds++;
2752 nano_seconds -= 1000000000;
2753 }
2754 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2755 return;
2756 } else if (time_step_ns < -15000000000LL) {
2757 /* convert to clock set */
2758 time_step_ns = -time_step_ns;
2759
2760 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2761 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2762 &remainder);
2763 nano_seconds_step = remainder;
2764 if (nano_seconds < nano_seconds_step) {
2765 unsigned_seconds--;
2766 nano_seconds += 1000000000;
2767 }
2768 nano_seconds -= nano_seconds_step;
2769 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2770 nano_seconds);
2771 return;
2772 }
2773
2774 /* do clock step */
2775 if (time_step_ns >= 0) {
2776 abs_time_step_ns = (u64)time_step_ns;
2777 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2778 &remainder);
2779 nano_seconds = remainder;
2780 } else {
2781 abs_time_step_ns = (u64)(-time_step_ns);
2782 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2783 &remainder));
2784 nano_seconds = remainder;
2785 if (nano_seconds > 0) {
2786 /* subtracting nano seconds is not allowed
2787 * convert to subtracting from seconds,
2788 * and adding to nanoseconds
2789 */
2790 seconds--;
2791 nano_seconds = (1000000000 - nano_seconds);
2792 }
2793 }
2794
2795 if (nano_seconds > 0) {
2796 /* add 8 ns to cover the likely normal increment */
2797 nano_seconds += 8;
2798 }
2799
2800 if (nano_seconds >= 1000000000) {
2801 /* carry into seconds */
2802 seconds++;
2803 nano_seconds -= 1000000000;
2804 }
2805
2806 while (seconds) {
2807 if (seconds > 0) {
2808 u32 adjustment_value = (u32)seconds;
2809 u16 adjustment_value_lo, adjustment_value_hi;
2810
2811 if (adjustment_value > 0xF)
2812 adjustment_value = 0xF;
2813
2814 adjustment_value_lo = adjustment_value & 0xffff;
2815 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2816
2817 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2818 adjustment_value_lo);
2819 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2820 PTP_LTC_STEP_ADJ_DIR_ |
2821 adjustment_value_hi);
2822 seconds -= ((s32)adjustment_value);
2823 } else {
2824 u32 adjustment_value = (u32)(-seconds);
2825 u16 adjustment_value_lo, adjustment_value_hi;
2826
2827 if (adjustment_value > 0xF)
2828 adjustment_value = 0xF;
2829
2830 adjustment_value_lo = adjustment_value & 0xffff;
2831 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2832
2833 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2834 adjustment_value_lo);
2835 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2836 adjustment_value_hi);
2837 seconds += ((s32)adjustment_value);
2838 }
2839 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2840 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2841 }
2842 if (nano_seconds) {
2843 u16 nano_seconds_lo;
2844 u16 nano_seconds_hi;
2845
2846 nano_seconds_lo = nano_seconds & 0xffff;
2847 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2848
2849 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2850 nano_seconds_lo);
2851 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2852 PTP_LTC_STEP_ADJ_DIR_ |
2853 nano_seconds_hi);
2854 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2855 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2856 }
2857 }
2858
lan8814_ptpci_adjtime(struct ptp_clock_info * ptpci,s64 delta)2859 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2860 {
2861 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2862 ptp_clock_info);
2863 struct phy_device *phydev = shared->phydev;
2864
2865 mutex_lock(&shared->shared_lock);
2866 lan8814_ptp_clock_step(phydev, delta);
2867 mutex_unlock(&shared->shared_lock);
2868
2869 return 0;
2870 }
2871
lan8814_ptpci_adjfine(struct ptp_clock_info * ptpci,long scaled_ppm)2872 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2873 {
2874 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2875 ptp_clock_info);
2876 struct phy_device *phydev = shared->phydev;
2877 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2878 bool positive = true;
2879 u32 kszphy_rate_adj;
2880
2881 if (scaled_ppm < 0) {
2882 scaled_ppm = -scaled_ppm;
2883 positive = false;
2884 }
2885
2886 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2887 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2888
2889 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2890 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2891
2892 if (positive)
2893 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2894
2895 mutex_lock(&shared->shared_lock);
2896 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2897 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2898 mutex_unlock(&shared->shared_lock);
2899
2900 return 0;
2901 }
2902
lan8814_get_sig_tx(struct sk_buff * skb,u16 * sig)2903 static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2904 {
2905 struct ptp_header *ptp_header;
2906 u32 type;
2907
2908 type = ptp_classify_raw(skb);
2909 ptp_header = ptp_parse_header(skb, type);
2910
2911 if (!ptp_header)
2912 return false;
2913
2914 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2915 return true;
2916 }
2917
lan8814_match_tx_skb(struct kszphy_ptp_priv * ptp_priv,u32 seconds,u32 nsec,u16 seq_id)2918 static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2919 u32 seconds, u32 nsec, u16 seq_id)
2920 {
2921 struct skb_shared_hwtstamps shhwtstamps;
2922 struct sk_buff *skb, *skb_tmp;
2923 unsigned long flags;
2924 bool ret = false;
2925 u16 skb_sig;
2926
2927 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2928 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2929 if (!lan8814_get_sig_tx(skb, &skb_sig))
2930 continue;
2931
2932 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2933 continue;
2934
2935 __skb_unlink(skb, &ptp_priv->tx_queue);
2936 ret = true;
2937 break;
2938 }
2939 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2940
2941 if (ret) {
2942 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2943 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2944 skb_complete_tx_timestamp(skb, &shhwtstamps);
2945 }
2946 }
2947
lan8814_dequeue_tx_skb(struct kszphy_ptp_priv * ptp_priv)2948 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2949 {
2950 struct phy_device *phydev = ptp_priv->phydev;
2951 u32 seconds, nsec;
2952 u16 seq_id;
2953
2954 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2955 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2956 }
2957
lan8814_get_tx_ts(struct kszphy_ptp_priv * ptp_priv)2958 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2959 {
2960 struct phy_device *phydev = ptp_priv->phydev;
2961 u32 reg;
2962
2963 do {
2964 lan8814_dequeue_tx_skb(ptp_priv);
2965
2966 /* If other timestamps are available in the FIFO,
2967 * process them.
2968 */
2969 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2970 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2971 }
2972
lan8814_match_skb(struct kszphy_ptp_priv * ptp_priv,struct lan8814_ptp_rx_ts * rx_ts)2973 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2974 struct lan8814_ptp_rx_ts *rx_ts)
2975 {
2976 struct skb_shared_hwtstamps *shhwtstamps;
2977 struct sk_buff *skb, *skb_tmp;
2978 unsigned long flags;
2979 bool ret = false;
2980 u16 skb_sig;
2981
2982 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2983 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2984 if (!lan8814_get_sig_rx(skb, &skb_sig))
2985 continue;
2986
2987 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2988 continue;
2989
2990 __skb_unlink(skb, &ptp_priv->rx_queue);
2991
2992 ret = true;
2993 break;
2994 }
2995 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2996
2997 if (ret) {
2998 shhwtstamps = skb_hwtstamps(skb);
2999 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3000 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
3001 netif_rx(skb);
3002 }
3003
3004 return ret;
3005 }
3006
lan8814_match_rx_ts(struct kszphy_ptp_priv * ptp_priv,struct lan8814_ptp_rx_ts * rx_ts)3007 static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
3008 struct lan8814_ptp_rx_ts *rx_ts)
3009 {
3010 unsigned long flags;
3011
3012 /* If we failed to match the skb add it to the queue for when
3013 * the frame will come
3014 */
3015 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
3016 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
3017 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
3018 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
3019 } else {
3020 kfree(rx_ts);
3021 }
3022 }
3023
lan8814_get_rx_ts(struct kszphy_ptp_priv * ptp_priv)3024 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
3025 {
3026 struct phy_device *phydev = ptp_priv->phydev;
3027 struct lan8814_ptp_rx_ts *rx_ts;
3028 u32 reg;
3029
3030 do {
3031 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
3032 if (!rx_ts)
3033 return;
3034
3035 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
3036 &rx_ts->seq_id);
3037 lan8814_match_rx_ts(ptp_priv, rx_ts);
3038
3039 /* If other timestamps are available in the FIFO,
3040 * process them.
3041 */
3042 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3043 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
3044 }
3045
lan8814_handle_ptp_interrupt(struct phy_device * phydev,u16 status)3046 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
3047 {
3048 struct kszphy_priv *priv = phydev->priv;
3049 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3050
3051 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
3052 lan8814_get_tx_ts(ptp_priv);
3053
3054 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
3055 lan8814_get_rx_ts(ptp_priv);
3056
3057 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
3058 lan8814_flush_fifo(phydev, true);
3059 skb_queue_purge(&ptp_priv->tx_queue);
3060 }
3061
3062 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
3063 lan8814_flush_fifo(phydev, false);
3064 skb_queue_purge(&ptp_priv->rx_queue);
3065 }
3066 }
3067
lan8804_config_init(struct phy_device * phydev)3068 static int lan8804_config_init(struct phy_device *phydev)
3069 {
3070 int val;
3071
3072 /* MDI-X setting for swap A,B transmit */
3073 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3074 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3075 val |= LAN8804_ALIGN_TX_A_B_SWAP;
3076 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3077
3078 /* Make sure that the PHY will not stop generating the clock when the
3079 * link partner goes down
3080 */
3081 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3082 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3083
3084 return 0;
3085 }
3086
lan8804_handle_interrupt(struct phy_device * phydev)3087 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3088 {
3089 int status;
3090
3091 status = phy_read(phydev, LAN8814_INTS);
3092 if (status < 0) {
3093 phy_error(phydev);
3094 return IRQ_NONE;
3095 }
3096
3097 if (status > 0)
3098 phy_trigger_machine(phydev);
3099
3100 return IRQ_HANDLED;
3101 }
3102
3103 #define LAN8804_OUTPUT_CONTROL 25
3104 #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3105 #define LAN8804_CONTROL 31
3106 #define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3107
lan8804_config_intr(struct phy_device * phydev)3108 static int lan8804_config_intr(struct phy_device *phydev)
3109 {
3110 int err;
3111
3112 /* This is an internal PHY of lan966x and is not possible to change the
3113 * polarity on the GIC found in lan966x, therefore change the polarity
3114 * of the interrupt in the PHY from being active low instead of active
3115 * high.
3116 */
3117 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3118
3119 /* By default interrupt buffer is open-drain in which case the interrupt
3120 * can be active only low. Therefore change the interrupt buffer to be
3121 * push-pull to be able to change interrupt polarity
3122 */
3123 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3124 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3125
3126 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3127 err = phy_read(phydev, LAN8814_INTS);
3128 if (err < 0)
3129 return err;
3130
3131 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3132 if (err)
3133 return err;
3134 } else {
3135 err = phy_write(phydev, LAN8814_INTC, 0);
3136 if (err)
3137 return err;
3138
3139 err = phy_read(phydev, LAN8814_INTS);
3140 if (err < 0)
3141 return err;
3142 }
3143
3144 return 0;
3145 }
3146
lan8814_handle_interrupt(struct phy_device * phydev)3147 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3148 {
3149 int ret = IRQ_NONE;
3150 int irq_status;
3151
3152 irq_status = phy_read(phydev, LAN8814_INTS);
3153 if (irq_status < 0) {
3154 phy_error(phydev);
3155 return IRQ_NONE;
3156 }
3157
3158 if (irq_status & LAN8814_INT_LINK) {
3159 phy_trigger_machine(phydev);
3160 ret = IRQ_HANDLED;
3161 }
3162
3163 while (true) {
3164 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3165 if (!irq_status)
3166 break;
3167
3168 lan8814_handle_ptp_interrupt(phydev, irq_status);
3169 ret = IRQ_HANDLED;
3170 }
3171
3172 return ret;
3173 }
3174
lan8814_ack_interrupt(struct phy_device * phydev)3175 static int lan8814_ack_interrupt(struct phy_device *phydev)
3176 {
3177 /* bit[12..0] int status, which is a read and clear register. */
3178 int rc;
3179
3180 rc = phy_read(phydev, LAN8814_INTS);
3181
3182 return (rc < 0) ? rc : 0;
3183 }
3184
lan8814_config_intr(struct phy_device * phydev)3185 static int lan8814_config_intr(struct phy_device *phydev)
3186 {
3187 int err;
3188
3189 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3190 LAN8814_INTR_CTRL_REG_POLARITY |
3191 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3192
3193 /* enable / disable interrupts */
3194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3195 err = lan8814_ack_interrupt(phydev);
3196 if (err)
3197 return err;
3198
3199 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3200 } else {
3201 err = phy_write(phydev, LAN8814_INTC, 0);
3202 if (err)
3203 return err;
3204
3205 err = lan8814_ack_interrupt(phydev);
3206 }
3207
3208 return err;
3209 }
3210
lan8814_ptp_init(struct phy_device * phydev)3211 static void lan8814_ptp_init(struct phy_device *phydev)
3212 {
3213 struct kszphy_priv *priv = phydev->priv;
3214 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3215 u32 temp;
3216
3217 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3218 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3219 return;
3220
3221 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3222
3223 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3224 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3225 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3226
3227 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3228 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3229 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3230
3231 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3232 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3233
3234 /* Removing default registers configs related to L2 and IP */
3235 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3236 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3237 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3238 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3239
3240 /* Disable checking for minorVersionPTP field */
3241 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3242 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3243 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3244 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3245
3246 skb_queue_head_init(&ptp_priv->tx_queue);
3247 skb_queue_head_init(&ptp_priv->rx_queue);
3248 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3249 spin_lock_init(&ptp_priv->rx_ts_lock);
3250
3251 ptp_priv->phydev = phydev;
3252
3253 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3254 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3255 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3256 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3257
3258 phydev->mii_ts = &ptp_priv->mii_ts;
3259 }
3260
lan8814_ptp_probe_once(struct phy_device * phydev)3261 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3262 {
3263 struct lan8814_shared_priv *shared = phydev->shared->priv;
3264
3265 /* Initialise shared lock for clock*/
3266 mutex_init(&shared->shared_lock);
3267
3268 shared->ptp_clock_info.owner = THIS_MODULE;
3269 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3270 shared->ptp_clock_info.max_adj = 31249999;
3271 shared->ptp_clock_info.n_alarm = 0;
3272 shared->ptp_clock_info.n_ext_ts = 0;
3273 shared->ptp_clock_info.n_pins = 0;
3274 shared->ptp_clock_info.pps = 0;
3275 shared->ptp_clock_info.pin_config = NULL;
3276 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3277 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3278 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3279 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3280 shared->ptp_clock_info.getcrosststamp = NULL;
3281
3282 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3283 &phydev->mdio.dev);
3284 if (IS_ERR(shared->ptp_clock)) {
3285 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3286 PTR_ERR(shared->ptp_clock));
3287 return -EINVAL;
3288 }
3289
3290 /* Check if PHC support is missing at the configuration level */
3291 if (!shared->ptp_clock)
3292 return 0;
3293
3294 phydev_dbg(phydev, "successfully registered ptp clock\n");
3295
3296 shared->phydev = phydev;
3297
3298 /* The EP.4 is shared between all the PHYs in the package and also it
3299 * can be accessed by any of the PHYs
3300 */
3301 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3302 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3303 PTP_OPERATING_MODE_STANDALONE_);
3304
3305 return 0;
3306 }
3307
lan8814_setup_led(struct phy_device * phydev,int val)3308 static void lan8814_setup_led(struct phy_device *phydev, int val)
3309 {
3310 int temp;
3311
3312 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3313
3314 if (val)
3315 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3316 else
3317 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3318
3319 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3320 }
3321
lan8814_config_init(struct phy_device * phydev)3322 static int lan8814_config_init(struct phy_device *phydev)
3323 {
3324 struct kszphy_priv *lan8814 = phydev->priv;
3325 int val;
3326
3327 /* Reset the PHY */
3328 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3329 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3330 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3331
3332 /* Disable ANEG with QSGMII PCS Host side */
3333 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3334 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3335 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3336
3337 /* MDI-X setting for swap A,B transmit */
3338 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3339 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3340 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3341 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3342
3343 if (lan8814->led_mode >= 0)
3344 lan8814_setup_led(phydev, lan8814->led_mode);
3345
3346 return 0;
3347 }
3348
3349 /* It is expected that there will not be any 'lan8814_take_coma_mode'
3350 * function called in suspend. Because the GPIO line can be shared, so if one of
3351 * the phys goes back in coma mode, then all the other PHYs will go, which is
3352 * wrong.
3353 */
lan8814_release_coma_mode(struct phy_device * phydev)3354 static int lan8814_release_coma_mode(struct phy_device *phydev)
3355 {
3356 struct gpio_desc *gpiod;
3357
3358 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3359 GPIOD_OUT_HIGH_OPEN_DRAIN |
3360 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3361 if (IS_ERR(gpiod))
3362 return PTR_ERR(gpiod);
3363
3364 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3365 gpiod_set_value_cansleep(gpiod, 0);
3366
3367 return 0;
3368 }
3369
lan8814_probe(struct phy_device * phydev)3370 static int lan8814_probe(struct phy_device *phydev)
3371 {
3372 const struct kszphy_type *type = phydev->drv->driver_data;
3373 struct kszphy_priv *priv;
3374 u16 addr;
3375 int err;
3376
3377 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3378 if (!priv)
3379 return -ENOMEM;
3380
3381 phydev->priv = priv;
3382
3383 priv->type = type;
3384
3385 kszphy_parse_led_mode(phydev);
3386
3387 /* Strap-in value for PHY address, below register read gives starting
3388 * phy address value
3389 */
3390 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3391 devm_phy_package_join(&phydev->mdio.dev, phydev,
3392 addr, sizeof(struct lan8814_shared_priv));
3393
3394 if (phy_package_init_once(phydev)) {
3395 err = lan8814_release_coma_mode(phydev);
3396 if (err)
3397 return err;
3398
3399 err = lan8814_ptp_probe_once(phydev);
3400 if (err)
3401 return err;
3402 }
3403
3404 lan8814_ptp_init(phydev);
3405
3406 return 0;
3407 }
3408
3409 #define LAN8841_MMD_TIMER_REG 0
3410 #define LAN8841_MMD0_REGISTER_17 17
3411 #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
3412 #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
3413 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
3414 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
3415 #define LAN8841_MMD_ANALOG_REG 28
3416 #define LAN8841_ANALOG_CONTROL_1 1
3417 #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
3418 #define LAN8841_ANALOG_CONTROL_10 13
3419 #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
3420 #define LAN8841_ANALOG_CONTROL_11 14
3421 #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
3422 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3423 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3424 #define LAN8841_BTRX_POWER_DOWN 70
3425 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
3426 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
3427 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
3428 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
3429 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
3430 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
3431 #define LAN8841_ADC_CHANNEL_MASK 198
3432 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
3433 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
3434 #define LAN8841_PTP_RX_VERSION 374
3435 #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
3436 #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
3437 #define LAN8841_PTP_TX_VERSION 438
3438 #define LAN8841_PTP_CMD_CTL 256
3439 #define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
3440 #define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
3441 #define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
3442 #define LAN8841_PTP_RX_PARSE_CONFIG 368
3443 #define LAN8841_PTP_TX_PARSE_CONFIG 432
3444 #define LAN8841_PTP_RX_MODE 381
3445 #define LAN8841_PTP_INSERT_TS_EN BIT(0)
3446 #define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
3447
lan8841_config_init(struct phy_device * phydev)3448 static int lan8841_config_init(struct phy_device *phydev)
3449 {
3450 int ret;
3451
3452 ret = ksz9131_config_init(phydev);
3453 if (ret)
3454 return ret;
3455
3456 /* Initialize the HW by resetting everything */
3457 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3458 LAN8841_PTP_CMD_CTL,
3459 LAN8841_PTP_CMD_CTL_PTP_RESET,
3460 LAN8841_PTP_CMD_CTL_PTP_RESET);
3461
3462 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3463 LAN8841_PTP_CMD_CTL,
3464 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3465 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3466
3467 /* Don't process any frames */
3468 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3469 LAN8841_PTP_RX_PARSE_CONFIG, 0);
3470 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3471 LAN8841_PTP_TX_PARSE_CONFIG, 0);
3472 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3473 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3474 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3475 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3476 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3477 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3478 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3479 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3480
3481 /* Disable checking for minorVersionPTP field */
3482 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3483 LAN8841_PTP_RX_VERSION, 0xff00);
3484 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3485 LAN8841_PTP_TX_VERSION, 0xff00);
3486
3487 /* 100BT Clause 40 improvenent errata */
3488 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3489 LAN8841_ANALOG_CONTROL_1,
3490 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3491 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3492 LAN8841_ANALOG_CONTROL_10,
3493 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3494
3495 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3496 * Magnetics
3497 */
3498 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3499 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3500 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3501 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3502 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3503 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3504 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3505 LAN8841_BTRX_POWER_DOWN,
3506 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3507 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3508 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3509 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3510 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3511 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3512 }
3513
3514 /* LDO Adjustment errata */
3515 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3516 LAN8841_ANALOG_CONTROL_11,
3517 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3518
3519 /* 100BT RGMII latency tuning errata */
3520 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3521 LAN8841_ADC_CHANNEL_MASK, 0x0);
3522 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3523 LAN8841_MMD0_REGISTER_17,
3524 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3525 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3526
3527 return 0;
3528 }
3529
3530 #define LAN8841_OUTPUT_CTRL 25
3531 #define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
3532 #define LAN8841_INT_PTP BIT(9)
3533
lan8841_config_intr(struct phy_device * phydev)3534 static int lan8841_config_intr(struct phy_device *phydev)
3535 {
3536 int err;
3537
3538 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3539 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3540
3541 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3542 err = phy_read(phydev, LAN8814_INTS);
3543 if (err < 0)
3544 return err;
3545
3546 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3547 * even if it PTP is not enabled. Because the underneath blocks
3548 * will not enable the PTP so we will never get the PTP
3549 * interrupt.
3550 */
3551 err = phy_write(phydev, LAN8814_INTC,
3552 LAN8814_INT_LINK | LAN8841_INT_PTP);
3553 } else {
3554 err = phy_write(phydev, LAN8814_INTC, 0);
3555 if (err)
3556 return err;
3557
3558 err = phy_read(phydev, LAN8814_INTS);
3559 if (err < 0)
3560 return err;
3561
3562 /* Getting a positive value doesn't mean that is an error, it
3563 * just indicates what was the status. Therefore make sure to
3564 * clear the value and say that there is no error.
3565 */
3566 err = 0;
3567 }
3568
3569 return err;
3570 }
3571
3572 #define LAN8841_PTP_TX_EGRESS_SEC_LO 453
3573 #define LAN8841_PTP_TX_EGRESS_SEC_HI 452
3574 #define LAN8841_PTP_TX_EGRESS_NS_LO 451
3575 #define LAN8841_PTP_TX_EGRESS_NS_HI 450
3576 #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
3577 #define LAN8841_PTP_TX_MSG_HEADER2 455
3578
lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv * ptp_priv,u32 * sec,u32 * nsec,u16 * seq)3579 static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3580 u32 *sec, u32 *nsec, u16 *seq)
3581 {
3582 struct phy_device *phydev = ptp_priv->phydev;
3583
3584 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3585 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3586 return false;
3587
3588 *nsec = ((*nsec & 0x3fff) << 16);
3589 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3590
3591 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3592 *sec = *sec << 16;
3593 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3594
3595 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3596
3597 return true;
3598 }
3599
lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv * ptp_priv)3600 static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3601 {
3602 u32 sec, nsec;
3603 u16 seq;
3604
3605 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3606 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3607 }
3608
3609 #define LAN8841_PTP_INT_STS 259
3610 #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3611 #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
3612 #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
3613
lan8841_ptp_flush_fifo(struct kszphy_ptp_priv * ptp_priv)3614 static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3615 {
3616 struct phy_device *phydev = ptp_priv->phydev;
3617 int i;
3618
3619 for (i = 0; i < FIFO_SIZE; ++i)
3620 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3621
3622 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3623 }
3624
3625 #define LAN8841_PTP_GPIO_CAP_STS 506
3626 #define LAN8841_PTP_GPIO_SEL 327
3627 #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
3628 #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
3629 #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
3630 #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
3631 #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
3632 #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
3633 #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
3634 #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
3635 #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
3636
lan8841_gpio_process_cap(struct kszphy_ptp_priv * ptp_priv)3637 static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3638 {
3639 struct phy_device *phydev = ptp_priv->phydev;
3640 struct ptp_clock_event ptp_event = {0};
3641 int pin, ret, tmp;
3642 s32 sec, nsec;
3643
3644 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3645 if (pin == -1)
3646 return;
3647
3648 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3649 if (tmp < 0)
3650 return;
3651
3652 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3653 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3654 if (ret)
3655 return;
3656
3657 mutex_lock(&ptp_priv->ptp_lock);
3658 if (tmp & BIT(pin)) {
3659 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3660 sec <<= 16;
3661 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3662
3663 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3664 nsec <<= 16;
3665 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3666 } else {
3667 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3668 sec <<= 16;
3669 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3670
3671 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3672 nsec <<= 16;
3673 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3674 }
3675 mutex_unlock(&ptp_priv->ptp_lock);
3676 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3677 if (ret)
3678 return;
3679
3680 ptp_event.index = 0;
3681 ptp_event.timestamp = ktime_set(sec, nsec);
3682 ptp_event.type = PTP_CLOCK_EXTTS;
3683 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3684 }
3685
lan8841_handle_ptp_interrupt(struct phy_device * phydev)3686 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3687 {
3688 struct kszphy_priv *priv = phydev->priv;
3689 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3690 u16 status;
3691
3692 do {
3693 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3694
3695 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3696 lan8841_ptp_process_tx_ts(ptp_priv);
3697
3698 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3699 lan8841_gpio_process_cap(ptp_priv);
3700
3701 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3702 lan8841_ptp_flush_fifo(ptp_priv);
3703 skb_queue_purge(&ptp_priv->tx_queue);
3704 }
3705
3706 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3707 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3708 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3709 }
3710
3711 #define LAN8841_INTS_PTP BIT(9)
3712
lan8841_handle_interrupt(struct phy_device * phydev)3713 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3714 {
3715 irqreturn_t ret = IRQ_NONE;
3716 int irq_status;
3717
3718 irq_status = phy_read(phydev, LAN8814_INTS);
3719 if (irq_status < 0) {
3720 phy_error(phydev);
3721 return IRQ_NONE;
3722 }
3723
3724 if (irq_status & LAN8814_INT_LINK) {
3725 phy_trigger_machine(phydev);
3726 ret = IRQ_HANDLED;
3727 }
3728
3729 if (irq_status & LAN8841_INTS_PTP) {
3730 lan8841_handle_ptp_interrupt(phydev);
3731 ret = IRQ_HANDLED;
3732 }
3733
3734 return ret;
3735 }
3736
lan8841_ts_info(struct mii_timestamper * mii_ts,struct ethtool_ts_info * info)3737 static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3738 struct ethtool_ts_info *info)
3739 {
3740 struct kszphy_ptp_priv *ptp_priv;
3741
3742 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3743
3744 info->phc_index = ptp_priv->ptp_clock ?
3745 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3746 if (info->phc_index == -1)
3747 return 0;
3748
3749 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3750 SOF_TIMESTAMPING_RX_HARDWARE |
3751 SOF_TIMESTAMPING_RAW_HARDWARE;
3752
3753 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3754 (1 << HWTSTAMP_TX_ON) |
3755 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3756
3757 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3758 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3759 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3760 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3761
3762 return 0;
3763 }
3764
3765 #define LAN8841_PTP_INT_EN 260
3766 #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
3767 #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
3768
lan8841_ptp_enable_processing(struct kszphy_ptp_priv * ptp_priv,bool enable)3769 static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3770 bool enable)
3771 {
3772 struct phy_device *phydev = ptp_priv->phydev;
3773
3774 if (enable) {
3775 /* Enable interrupts on the TX side */
3776 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3777 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3778 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3779 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3780 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3781
3782 /* Enable the modification of the frame on RX side,
3783 * this will add the ns and 2 bits of sec in the reserved field
3784 * of the PTP header
3785 */
3786 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3787 LAN8841_PTP_RX_MODE,
3788 LAN8841_PTP_INSERT_TS_EN |
3789 LAN8841_PTP_INSERT_TS_32BIT,
3790 LAN8841_PTP_INSERT_TS_EN |
3791 LAN8841_PTP_INSERT_TS_32BIT);
3792
3793 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3794 } else {
3795 /* Disable interrupts on the TX side */
3796 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3797 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3798 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3799
3800 /* Disable modification of the RX frames */
3801 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3802 LAN8841_PTP_RX_MODE,
3803 LAN8841_PTP_INSERT_TS_EN |
3804 LAN8841_PTP_INSERT_TS_32BIT, 0);
3805
3806 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3807 }
3808 }
3809
3810 #define LAN8841_PTP_RX_TIMESTAMP_EN 379
3811 #define LAN8841_PTP_TX_TIMESTAMP_EN 443
3812 #define LAN8841_PTP_TX_MOD 445
3813
lan8841_hwtstamp(struct mii_timestamper * mii_ts,struct ifreq * ifr)3814 static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
3815 {
3816 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3817 struct phy_device *phydev = ptp_priv->phydev;
3818 struct hwtstamp_config config;
3819 int txcfg = 0, rxcfg = 0;
3820 int pkt_ts_enable;
3821
3822 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3823 return -EFAULT;
3824
3825 ptp_priv->hwts_tx_type = config.tx_type;
3826 ptp_priv->rx_filter = config.rx_filter;
3827
3828 switch (config.rx_filter) {
3829 case HWTSTAMP_FILTER_NONE:
3830 ptp_priv->layer = 0;
3831 ptp_priv->version = 0;
3832 break;
3833 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3834 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3835 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3836 ptp_priv->layer = PTP_CLASS_L4;
3837 ptp_priv->version = PTP_CLASS_V2;
3838 break;
3839 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3840 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3841 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3842 ptp_priv->layer = PTP_CLASS_L2;
3843 ptp_priv->version = PTP_CLASS_V2;
3844 break;
3845 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3846 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3847 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3848 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3849 ptp_priv->version = PTP_CLASS_V2;
3850 break;
3851 default:
3852 return -ERANGE;
3853 }
3854
3855 /* Setup parsing of the frames and enable the timestamping for ptp
3856 * frames
3857 */
3858 if (ptp_priv->layer & PTP_CLASS_L2) {
3859 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3860 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3861 } else if (ptp_priv->layer & PTP_CLASS_L4) {
3862 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3863 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3864 }
3865
3866 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3867 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3868
3869 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3870 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3871 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3872 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3873
3874 /* Enable / disable of the TX timestamp in the SYNC frames */
3875 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3876 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3877 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3878 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3879
3880 /* Now enable/disable the timestamping */
3881 lan8841_ptp_enable_processing(ptp_priv,
3882 config.rx_filter != HWTSTAMP_FILTER_NONE);
3883
3884 skb_queue_purge(&ptp_priv->tx_queue);
3885
3886 lan8841_ptp_flush_fifo(ptp_priv);
3887
3888 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
3889 }
3890
lan8841_rxtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)3891 static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3892 struct sk_buff *skb, int type)
3893 {
3894 struct kszphy_ptp_priv *ptp_priv =
3895 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3896 struct ptp_header *header = ptp_parse_header(skb, type);
3897 struct skb_shared_hwtstamps *shhwtstamps;
3898 struct timespec64 ts;
3899 unsigned long flags;
3900 u32 ts_header;
3901
3902 if (!header)
3903 return false;
3904
3905 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3906 type == PTP_CLASS_NONE)
3907 return false;
3908
3909 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3910 return false;
3911
3912 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3913 ts.tv_sec = ptp_priv->seconds;
3914 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3915 ts_header = __be32_to_cpu(header->reserved2);
3916
3917 shhwtstamps = skb_hwtstamps(skb);
3918 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3919
3920 /* Check for any wrap arounds for the second part */
3921 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3922 ts.tv_sec -= GENMASK(1, 0) + 1;
3923 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3924 ts.tv_sec += 1;
3925
3926 shhwtstamps->hwtstamp =
3927 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3928 ts_header & GENMASK(29, 0));
3929 header->reserved2 = 0;
3930
3931 netif_rx(skb);
3932
3933 return true;
3934 }
3935
3936 #define LAN8841_EVENT_A 0
3937 #define LAN8841_EVENT_B 1
3938 #define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
3939 #define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
3940 #define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
3941 #define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
3942
lan8841_ptp_set_target(struct kszphy_ptp_priv * ptp_priv,u8 event,s64 sec,u32 nsec)3943 static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3944 s64 sec, u32 nsec)
3945 {
3946 struct phy_device *phydev = ptp_priv->phydev;
3947 int ret;
3948
3949 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3950 upper_16_bits(sec));
3951 if (ret)
3952 return ret;
3953
3954 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3955 lower_16_bits(sec));
3956 if (ret)
3957 return ret;
3958
3959 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3960 upper_16_bits(nsec));
3961 if (ret)
3962 return ret;
3963
3964 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3965 lower_16_bits(nsec));
3966 }
3967
3968 #define LAN8841_BUFFER_TIME 2
3969
lan8841_ptp_update_target(struct kszphy_ptp_priv * ptp_priv,const struct timespec64 * ts)3970 static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3971 const struct timespec64 *ts)
3972 {
3973 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3974 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3975 }
3976
3977 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
3978 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
3979 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
3980 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
3981
lan8841_ptp_set_reload(struct kszphy_ptp_priv * ptp_priv,u8 event,s64 sec,u32 nsec)3982 static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3983 s64 sec, u32 nsec)
3984 {
3985 struct phy_device *phydev = ptp_priv->phydev;
3986 int ret;
3987
3988 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3989 upper_16_bits(sec));
3990 if (ret)
3991 return ret;
3992
3993 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3994 lower_16_bits(sec));
3995 if (ret)
3996 return ret;
3997
3998 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3999 upper_16_bits(nsec));
4000 if (ret)
4001 return ret;
4002
4003 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
4004 lower_16_bits(nsec));
4005 }
4006
4007 #define LAN8841_PTP_LTC_SET_SEC_HI 262
4008 #define LAN8841_PTP_LTC_SET_SEC_MID 263
4009 #define LAN8841_PTP_LTC_SET_SEC_LO 264
4010 #define LAN8841_PTP_LTC_SET_NS_HI 265
4011 #define LAN8841_PTP_LTC_SET_NS_LO 266
4012 #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
4013
lan8841_ptp_settime64(struct ptp_clock_info * ptp,const struct timespec64 * ts)4014 static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
4015 const struct timespec64 *ts)
4016 {
4017 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4018 ptp_clock_info);
4019 struct phy_device *phydev = ptp_priv->phydev;
4020 unsigned long flags;
4021 int ret;
4022
4023 /* Set the value to be stored */
4024 mutex_lock(&ptp_priv->ptp_lock);
4025 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
4026 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
4027 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
4028 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
4029 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
4030
4031 /* Set the command to load the LTC */
4032 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4033 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
4034 ret = lan8841_ptp_update_target(ptp_priv, ts);
4035 mutex_unlock(&ptp_priv->ptp_lock);
4036
4037 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4038 ptp_priv->seconds = ts->tv_sec;
4039 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4040
4041 return ret;
4042 }
4043
4044 #define LAN8841_PTP_LTC_RD_SEC_HI 358
4045 #define LAN8841_PTP_LTC_RD_SEC_MID 359
4046 #define LAN8841_PTP_LTC_RD_SEC_LO 360
4047 #define LAN8841_PTP_LTC_RD_NS_HI 361
4048 #define LAN8841_PTP_LTC_RD_NS_LO 362
4049 #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
4050
lan8841_ptp_gettime64(struct ptp_clock_info * ptp,struct timespec64 * ts)4051 static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
4052 struct timespec64 *ts)
4053 {
4054 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4055 ptp_clock_info);
4056 struct phy_device *phydev = ptp_priv->phydev;
4057 time64_t s;
4058 s64 ns;
4059
4060 mutex_lock(&ptp_priv->ptp_lock);
4061 /* Issue the command to read the LTC */
4062 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4063 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4064
4065 /* Read the LTC */
4066 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4067 s <<= 16;
4068 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4069 s <<= 16;
4070 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4071
4072 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
4073 ns <<= 16;
4074 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
4075 mutex_unlock(&ptp_priv->ptp_lock);
4076
4077 set_normalized_timespec64(ts, s, ns);
4078 return 0;
4079 }
4080
lan8841_ptp_getseconds(struct ptp_clock_info * ptp,struct timespec64 * ts)4081 static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4082 struct timespec64 *ts)
4083 {
4084 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4085 ptp_clock_info);
4086 struct phy_device *phydev = ptp_priv->phydev;
4087 time64_t s;
4088
4089 mutex_lock(&ptp_priv->ptp_lock);
4090 /* Issue the command to read the LTC */
4091 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4092 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4093
4094 /* Read the LTC */
4095 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4096 s <<= 16;
4097 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4098 s <<= 16;
4099 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4100 mutex_unlock(&ptp_priv->ptp_lock);
4101
4102 set_normalized_timespec64(ts, s, 0);
4103 }
4104
4105 #define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4106 #define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4107 #define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4108 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4109 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4110
lan8841_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)4111 static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4112 {
4113 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4114 ptp_clock_info);
4115 struct phy_device *phydev = ptp_priv->phydev;
4116 struct timespec64 ts;
4117 bool add = true;
4118 u32 nsec;
4119 s32 sec;
4120 int ret;
4121
4122 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4123 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4124 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4125 * increment so the value can be bigger than 15 sec. Therefore limit the
4126 * possible adjustments so we will not have these corner cases
4127 */
4128 if (delta > 10000000000LL || delta < -10000000000LL) {
4129 /* The timeadjustment is too big, so fall back using set time */
4130 u64 now;
4131
4132 ptp->gettime64(ptp, &ts);
4133
4134 now = ktime_to_ns(timespec64_to_ktime(ts));
4135 ts = ns_to_timespec64(now + delta);
4136
4137 ptp->settime64(ptp, &ts);
4138 return 0;
4139 }
4140
4141 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4142 if (delta < 0 && nsec != 0) {
4143 /* It is not allowed to adjust low the nsec part, therefore
4144 * subtract more from second part and add to nanosecond such
4145 * that would roll over, so the second part will increase
4146 */
4147 sec--;
4148 nsec = NSEC_PER_SEC - nsec;
4149 }
4150
4151 /* Calculate the adjustments and the direction */
4152 if (delta < 0)
4153 add = false;
4154
4155 if (nsec > 0)
4156 /* add 8 ns to cover the likely normal increment */
4157 nsec += 8;
4158
4159 if (nsec >= NSEC_PER_SEC) {
4160 /* carry into seconds */
4161 sec++;
4162 nsec -= NSEC_PER_SEC;
4163 }
4164
4165 mutex_lock(&ptp_priv->ptp_lock);
4166 if (sec) {
4167 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4168 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4169 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4170 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4171 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4172 }
4173
4174 if (nsec) {
4175 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4176 nsec & 0xffff);
4177 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4178 (nsec >> 16) & 0x3fff);
4179 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4180 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4181 }
4182 mutex_unlock(&ptp_priv->ptp_lock);
4183
4184 /* Update the target clock */
4185 ptp->gettime64(ptp, &ts);
4186 mutex_lock(&ptp_priv->ptp_lock);
4187 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4188 mutex_unlock(&ptp_priv->ptp_lock);
4189
4190 return ret;
4191 }
4192
4193 #define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4194 #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4195 #define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4196
lan8841_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)4197 static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4198 {
4199 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4200 ptp_clock_info);
4201 struct phy_device *phydev = ptp_priv->phydev;
4202 bool faster = true;
4203 u32 rate;
4204
4205 if (!scaled_ppm)
4206 return 0;
4207
4208 if (scaled_ppm < 0) {
4209 scaled_ppm = -scaled_ppm;
4210 faster = false;
4211 }
4212
4213 rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4214 rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4215
4216 mutex_lock(&ptp_priv->ptp_lock);
4217 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4218 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4219 : upper_16_bits(rate) & 0x3fff);
4220 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4221 mutex_unlock(&ptp_priv->ptp_lock);
4222
4223 return 0;
4224 }
4225
lan8841_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)4226 static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4227 enum ptp_pin_function func, unsigned int chan)
4228 {
4229 switch (func) {
4230 case PTP_PF_NONE:
4231 case PTP_PF_PEROUT:
4232 case PTP_PF_EXTTS:
4233 break;
4234 default:
4235 return -1;
4236 }
4237
4238 return 0;
4239 }
4240
4241 #define LAN8841_PTP_GPIO_NUM 10
4242 #define LAN8841_GPIO_EN 128
4243 #define LAN8841_GPIO_DIR 129
4244 #define LAN8841_GPIO_BUF 130
4245
lan8841_ptp_perout_off(struct kszphy_ptp_priv * ptp_priv,int pin)4246 static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4247 {
4248 struct phy_device *phydev = ptp_priv->phydev;
4249 int ret;
4250
4251 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4252 if (ret)
4253 return ret;
4254
4255 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4256 if (ret)
4257 return ret;
4258
4259 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4260 }
4261
lan8841_ptp_perout_on(struct kszphy_ptp_priv * ptp_priv,int pin)4262 static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4263 {
4264 struct phy_device *phydev = ptp_priv->phydev;
4265 int ret;
4266
4267 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4268 if (ret)
4269 return ret;
4270
4271 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4272 if (ret)
4273 return ret;
4274
4275 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4276 }
4277
4278 #define LAN8841_GPIO_DATA_SEL1 131
4279 #define LAN8841_GPIO_DATA_SEL2 132
4280 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4281 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4282 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4283 #define LAN8841_PTP_GENERAL_CONFIG 257
4284 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4285 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4286 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4287 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4288 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4289 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4290
lan8841_ptp_remove_event(struct kszphy_ptp_priv * ptp_priv,int pin,u8 event)4291 static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4292 u8 event)
4293 {
4294 struct phy_device *phydev = ptp_priv->phydev;
4295 u16 tmp;
4296 int ret;
4297
4298 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4299 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4300 * depending on the pin, it requires to read a different register
4301 */
4302 if (pin < 5) {
4303 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4304 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4305 } else {
4306 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4307 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4308 }
4309 if (ret)
4310 return ret;
4311
4312 /* Disable the event */
4313 if (event == LAN8841_EVENT_A)
4314 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4315 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4316 else
4317 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4318 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4319 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4320 }
4321
lan8841_ptp_enable_event(struct kszphy_ptp_priv * ptp_priv,int pin,u8 event,int pulse_width)4322 static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4323 u8 event, int pulse_width)
4324 {
4325 struct phy_device *phydev = ptp_priv->phydev;
4326 u16 tmp;
4327 int ret;
4328
4329 /* Enable the event */
4330 if (event == LAN8841_EVENT_A)
4331 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4332 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4333 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4334 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4335 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4336 else
4337 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4338 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4339 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4340 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4341 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4342 if (ret)
4343 return ret;
4344
4345 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4346 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4347 * depending on the pin, it requires to read a different register
4348 */
4349 if (event == LAN8841_EVENT_A)
4350 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4351 else
4352 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4353
4354 if (pin < 5)
4355 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4356 tmp << (3 * pin));
4357 else
4358 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4359 tmp << (3 * (pin - 5)));
4360
4361 return ret;
4362 }
4363
4364 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
4365 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
4366 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
4367 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
4368 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
4369 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
4370 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
4371 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
4372 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
4373 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
4374 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
4375 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
4376 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
4377 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
4378
lan8841_ptp_perout(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)4379 static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4380 struct ptp_clock_request *rq, int on)
4381 {
4382 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4383 ptp_clock_info);
4384 struct phy_device *phydev = ptp_priv->phydev;
4385 struct timespec64 ts_on, ts_period;
4386 s64 on_nsec, period_nsec;
4387 int pulse_width;
4388 int pin;
4389 int ret;
4390
4391 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4392 return -EOPNOTSUPP;
4393
4394 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4395 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4396 return -EINVAL;
4397
4398 if (!on) {
4399 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4400 if (ret)
4401 return ret;
4402
4403 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4404 }
4405
4406 ts_on.tv_sec = rq->perout.on.sec;
4407 ts_on.tv_nsec = rq->perout.on.nsec;
4408 on_nsec = timespec64_to_ns(&ts_on);
4409
4410 ts_period.tv_sec = rq->perout.period.sec;
4411 ts_period.tv_nsec = rq->perout.period.nsec;
4412 period_nsec = timespec64_to_ns(&ts_period);
4413
4414 if (period_nsec < 200) {
4415 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4416 phydev_name(phydev));
4417 return -EOPNOTSUPP;
4418 }
4419
4420 if (on_nsec >= period_nsec) {
4421 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4422 phydev_name(phydev));
4423 return -EINVAL;
4424 }
4425
4426 switch (on_nsec) {
4427 case 200000000:
4428 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4429 break;
4430 case 100000000:
4431 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4432 break;
4433 case 50000000:
4434 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4435 break;
4436 case 10000000:
4437 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4438 break;
4439 case 5000000:
4440 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4441 break;
4442 case 1000000:
4443 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4444 break;
4445 case 500000:
4446 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4447 break;
4448 case 100000:
4449 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4450 break;
4451 case 50000:
4452 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4453 break;
4454 case 10000:
4455 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4456 break;
4457 case 5000:
4458 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4459 break;
4460 case 1000:
4461 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4462 break;
4463 case 500:
4464 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4465 break;
4466 case 100:
4467 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4468 break;
4469 default:
4470 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4471 phydev_name(phydev));
4472 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4473 break;
4474 }
4475
4476 mutex_lock(&ptp_priv->ptp_lock);
4477 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4478 rq->perout.start.nsec);
4479 mutex_unlock(&ptp_priv->ptp_lock);
4480 if (ret)
4481 return ret;
4482
4483 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4484 rq->perout.period.nsec);
4485 if (ret)
4486 return ret;
4487
4488 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4489 pulse_width);
4490 if (ret)
4491 return ret;
4492
4493 ret = lan8841_ptp_perout_on(ptp_priv, pin);
4494 if (ret)
4495 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4496
4497 return ret;
4498 }
4499
4500 #define LAN8841_PTP_GPIO_CAP_EN 496
4501 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
4502 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
4503 #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
4504
lan8841_ptp_extts_on(struct kszphy_ptp_priv * ptp_priv,int pin,u32 flags)4505 static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4506 u32 flags)
4507 {
4508 struct phy_device *phydev = ptp_priv->phydev;
4509 u16 tmp = 0;
4510 int ret;
4511
4512 /* Set GPIO to be intput */
4513 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4514 if (ret)
4515 return ret;
4516
4517 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4518 if (ret)
4519 return ret;
4520
4521 /* Enable capture on the edges of the pin */
4522 if (flags & PTP_RISING_EDGE)
4523 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4524 if (flags & PTP_FALLING_EDGE)
4525 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4526 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4527 if (ret)
4528 return ret;
4529
4530 /* Enable interrupt */
4531 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4532 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4533 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4534 }
4535
lan8841_ptp_extts_off(struct kszphy_ptp_priv * ptp_priv,int pin)4536 static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4537 {
4538 struct phy_device *phydev = ptp_priv->phydev;
4539 int ret;
4540
4541 /* Set GPIO to be output */
4542 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4543 if (ret)
4544 return ret;
4545
4546 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4547 if (ret)
4548 return ret;
4549
4550 /* Disable capture on both of the edges */
4551 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4552 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4553 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4554 0);
4555 if (ret)
4556 return ret;
4557
4558 /* Disable interrupt */
4559 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4560 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4561 0);
4562 }
4563
lan8841_ptp_extts(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)4564 static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4565 struct ptp_clock_request *rq, int on)
4566 {
4567 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4568 ptp_clock_info);
4569 int pin;
4570 int ret;
4571
4572 /* Reject requests with unsupported flags */
4573 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4574 PTP_EXTTS_EDGES |
4575 PTP_STRICT_FLAGS))
4576 return -EOPNOTSUPP;
4577
4578 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4579 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4580 return -EINVAL;
4581
4582 mutex_lock(&ptp_priv->ptp_lock);
4583 if (on)
4584 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4585 else
4586 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4587 mutex_unlock(&ptp_priv->ptp_lock);
4588
4589 return ret;
4590 }
4591
lan8841_ptp_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)4592 static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4593 struct ptp_clock_request *rq, int on)
4594 {
4595 switch (rq->type) {
4596 case PTP_CLK_REQ_EXTTS:
4597 return lan8841_ptp_extts(ptp, rq, on);
4598 case PTP_CLK_REQ_PEROUT:
4599 return lan8841_ptp_perout(ptp, rq, on);
4600 default:
4601 return -EOPNOTSUPP;
4602 }
4603
4604 return 0;
4605 }
4606
lan8841_ptp_do_aux_work(struct ptp_clock_info * ptp)4607 static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4608 {
4609 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4610 ptp_clock_info);
4611 struct timespec64 ts;
4612 unsigned long flags;
4613
4614 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4615
4616 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4617 ptp_priv->seconds = ts.tv_sec;
4618 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4619
4620 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4621 }
4622
4623 static struct ptp_clock_info lan8841_ptp_clock_info = {
4624 .owner = THIS_MODULE,
4625 .name = "lan8841 ptp",
4626 .max_adj = 31249999,
4627 .gettime64 = lan8841_ptp_gettime64,
4628 .settime64 = lan8841_ptp_settime64,
4629 .adjtime = lan8841_ptp_adjtime,
4630 .adjfine = lan8841_ptp_adjfine,
4631 .verify = lan8841_ptp_verify,
4632 .enable = lan8841_ptp_enable,
4633 .do_aux_work = lan8841_ptp_do_aux_work,
4634 .n_per_out = LAN8841_PTP_GPIO_NUM,
4635 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
4636 .n_pins = LAN8841_PTP_GPIO_NUM,
4637 };
4638
4639 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4640 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4641
lan8841_probe(struct phy_device * phydev)4642 static int lan8841_probe(struct phy_device *phydev)
4643 {
4644 struct kszphy_ptp_priv *ptp_priv;
4645 struct kszphy_priv *priv;
4646 int err;
4647
4648 err = kszphy_probe(phydev);
4649 if (err)
4650 return err;
4651
4652 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4653 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4654 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4655 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4656
4657 /* Register the clock */
4658 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4659 return 0;
4660
4661 priv = phydev->priv;
4662 ptp_priv = &priv->ptp_priv;
4663
4664 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4665 LAN8841_PTP_GPIO_NUM,
4666 sizeof(*ptp_priv->pin_config),
4667 GFP_KERNEL);
4668 if (!ptp_priv->pin_config)
4669 return -ENOMEM;
4670
4671 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4672 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4673
4674 snprintf(p->name, sizeof(p->name), "pin%d", i);
4675 p->index = i;
4676 p->func = PTP_PF_NONE;
4677 }
4678
4679 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4680 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4681 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4682 &phydev->mdio.dev);
4683 if (IS_ERR(ptp_priv->ptp_clock)) {
4684 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4685 PTR_ERR(ptp_priv->ptp_clock));
4686 return -EINVAL;
4687 }
4688
4689 if (!ptp_priv->ptp_clock)
4690 return 0;
4691
4692 /* Initialize the SW */
4693 skb_queue_head_init(&ptp_priv->tx_queue);
4694 ptp_priv->phydev = phydev;
4695 mutex_init(&ptp_priv->ptp_lock);
4696 spin_lock_init(&ptp_priv->seconds_lock);
4697
4698 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4699 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4700 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4701 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4702
4703 phydev->mii_ts = &ptp_priv->mii_ts;
4704
4705 return 0;
4706 }
4707
lan8841_suspend(struct phy_device * phydev)4708 static int lan8841_suspend(struct phy_device *phydev)
4709 {
4710 struct kszphy_priv *priv = phydev->priv;
4711 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4712
4713 if (ptp_priv->ptp_clock)
4714 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4715
4716 return genphy_suspend(phydev);
4717 }
4718
4719 static struct phy_driver ksphy_driver[] = {
4720 {
4721 .phy_id = PHY_ID_KS8737,
4722 .phy_id_mask = MICREL_PHY_ID_MASK,
4723 .name = "Micrel KS8737",
4724 /* PHY_BASIC_FEATURES */
4725 .driver_data = &ks8737_type,
4726 .probe = kszphy_probe,
4727 .config_init = kszphy_config_init,
4728 .config_intr = kszphy_config_intr,
4729 .handle_interrupt = kszphy_handle_interrupt,
4730 .suspend = kszphy_suspend,
4731 .resume = kszphy_resume,
4732 }, {
4733 .phy_id = PHY_ID_KSZ8021,
4734 .phy_id_mask = 0x00ffffff,
4735 .name = "Micrel KSZ8021 or KSZ8031",
4736 /* PHY_BASIC_FEATURES */
4737 .driver_data = &ksz8021_type,
4738 .probe = kszphy_probe,
4739 .config_init = kszphy_config_init,
4740 .config_intr = kszphy_config_intr,
4741 .handle_interrupt = kszphy_handle_interrupt,
4742 .get_sset_count = kszphy_get_sset_count,
4743 .get_strings = kszphy_get_strings,
4744 .get_stats = kszphy_get_stats,
4745 .suspend = kszphy_suspend,
4746 .resume = kszphy_resume,
4747 }, {
4748 .phy_id = PHY_ID_KSZ8031,
4749 .phy_id_mask = 0x00ffffff,
4750 .name = "Micrel KSZ8031",
4751 /* PHY_BASIC_FEATURES */
4752 .driver_data = &ksz8021_type,
4753 .probe = kszphy_probe,
4754 .config_init = kszphy_config_init,
4755 .config_intr = kszphy_config_intr,
4756 .handle_interrupt = kszphy_handle_interrupt,
4757 .get_sset_count = kszphy_get_sset_count,
4758 .get_strings = kszphy_get_strings,
4759 .get_stats = kszphy_get_stats,
4760 .suspend = kszphy_suspend,
4761 .resume = kszphy_resume,
4762 }, {
4763 .phy_id = PHY_ID_KSZ8041,
4764 .phy_id_mask = MICREL_PHY_ID_MASK,
4765 .name = "Micrel KSZ8041",
4766 /* PHY_BASIC_FEATURES */
4767 .driver_data = &ksz8041_type,
4768 .probe = kszphy_probe,
4769 .config_init = ksz8041_config_init,
4770 .config_aneg = ksz8041_config_aneg,
4771 .config_intr = kszphy_config_intr,
4772 .handle_interrupt = kszphy_handle_interrupt,
4773 .get_sset_count = kszphy_get_sset_count,
4774 .get_strings = kszphy_get_strings,
4775 .get_stats = kszphy_get_stats,
4776 /* No suspend/resume callbacks because of errata DS80000700A,
4777 * receiver error following software power down.
4778 */
4779 }, {
4780 .phy_id = PHY_ID_KSZ8041RNLI,
4781 .phy_id_mask = MICREL_PHY_ID_MASK,
4782 .name = "Micrel KSZ8041RNLI",
4783 /* PHY_BASIC_FEATURES */
4784 .driver_data = &ksz8041_type,
4785 .probe = kszphy_probe,
4786 .config_init = kszphy_config_init,
4787 .config_intr = kszphy_config_intr,
4788 .handle_interrupt = kszphy_handle_interrupt,
4789 .get_sset_count = kszphy_get_sset_count,
4790 .get_strings = kszphy_get_strings,
4791 .get_stats = kszphy_get_stats,
4792 .suspend = kszphy_suspend,
4793 .resume = kszphy_resume,
4794 }, {
4795 .name = "Micrel KSZ8051",
4796 /* PHY_BASIC_FEATURES */
4797 .driver_data = &ksz8051_type,
4798 .probe = kszphy_probe,
4799 .config_init = kszphy_config_init,
4800 .config_intr = kszphy_config_intr,
4801 .handle_interrupt = kszphy_handle_interrupt,
4802 .get_sset_count = kszphy_get_sset_count,
4803 .get_strings = kszphy_get_strings,
4804 .get_stats = kszphy_get_stats,
4805 .match_phy_device = ksz8051_match_phy_device,
4806 .suspend = kszphy_suspend,
4807 .resume = kszphy_resume,
4808 }, {
4809 .phy_id = PHY_ID_KSZ8001,
4810 .name = "Micrel KSZ8001 or KS8721",
4811 .phy_id_mask = 0x00fffffc,
4812 /* PHY_BASIC_FEATURES */
4813 .driver_data = &ksz8041_type,
4814 .probe = kszphy_probe,
4815 .config_init = kszphy_config_init,
4816 .config_intr = kszphy_config_intr,
4817 .handle_interrupt = kszphy_handle_interrupt,
4818 .get_sset_count = kszphy_get_sset_count,
4819 .get_strings = kszphy_get_strings,
4820 .get_stats = kszphy_get_stats,
4821 .suspend = kszphy_suspend,
4822 .resume = kszphy_resume,
4823 }, {
4824 .phy_id = PHY_ID_KSZ8081,
4825 .name = "Micrel KSZ8081 or KSZ8091",
4826 .phy_id_mask = MICREL_PHY_ID_MASK,
4827 .flags = PHY_POLL_CABLE_TEST,
4828 /* PHY_BASIC_FEATURES */
4829 .driver_data = &ksz8081_type,
4830 .probe = kszphy_probe,
4831 .config_init = ksz8081_config_init,
4832 .soft_reset = genphy_soft_reset,
4833 .config_aneg = ksz8081_config_aneg,
4834 .read_status = ksz8081_read_status,
4835 .config_intr = kszphy_config_intr,
4836 .handle_interrupt = kszphy_handle_interrupt,
4837 .get_sset_count = kszphy_get_sset_count,
4838 .get_strings = kszphy_get_strings,
4839 .get_stats = kszphy_get_stats,
4840 .suspend = kszphy_suspend,
4841 .resume = kszphy_resume,
4842 .cable_test_start = ksz886x_cable_test_start,
4843 .cable_test_get_status = ksz886x_cable_test_get_status,
4844 }, {
4845 .phy_id = PHY_ID_KSZ8061,
4846 .name = "Micrel KSZ8061",
4847 .phy_id_mask = MICREL_PHY_ID_MASK,
4848 /* PHY_BASIC_FEATURES */
4849 .probe = kszphy_probe,
4850 .config_init = ksz8061_config_init,
4851 .soft_reset = genphy_soft_reset,
4852 .config_intr = kszphy_config_intr,
4853 .handle_interrupt = kszphy_handle_interrupt,
4854 .suspend = kszphy_suspend,
4855 .resume = ksz8061_resume,
4856 }, {
4857 .phy_id = PHY_ID_KSZ9021,
4858 .phy_id_mask = 0x000ffffe,
4859 .name = "Micrel KSZ9021 Gigabit PHY",
4860 /* PHY_GBIT_FEATURES */
4861 .driver_data = &ksz9021_type,
4862 .probe = kszphy_probe,
4863 .get_features = ksz9031_get_features,
4864 .config_init = ksz9021_config_init,
4865 .config_intr = kszphy_config_intr,
4866 .handle_interrupt = kszphy_handle_interrupt,
4867 .get_sset_count = kszphy_get_sset_count,
4868 .get_strings = kszphy_get_strings,
4869 .get_stats = kszphy_get_stats,
4870 .suspend = kszphy_suspend,
4871 .resume = kszphy_resume,
4872 .read_mmd = genphy_read_mmd_unsupported,
4873 .write_mmd = genphy_write_mmd_unsupported,
4874 }, {
4875 .phy_id = PHY_ID_KSZ9031,
4876 .phy_id_mask = MICREL_PHY_ID_MASK,
4877 .name = "Micrel KSZ9031 Gigabit PHY",
4878 .flags = PHY_POLL_CABLE_TEST,
4879 .driver_data = &ksz9021_type,
4880 .probe = kszphy_probe,
4881 .get_features = ksz9031_get_features,
4882 .config_init = ksz9031_config_init,
4883 .soft_reset = genphy_soft_reset,
4884 .read_status = ksz9031_read_status,
4885 .config_intr = kszphy_config_intr,
4886 .handle_interrupt = kszphy_handle_interrupt,
4887 .get_sset_count = kszphy_get_sset_count,
4888 .get_strings = kszphy_get_strings,
4889 .get_stats = kszphy_get_stats,
4890 .suspend = kszphy_suspend,
4891 .resume = kszphy_resume,
4892 .cable_test_start = ksz9x31_cable_test_start,
4893 .cable_test_get_status = ksz9x31_cable_test_get_status,
4894 }, {
4895 .phy_id = PHY_ID_LAN8814,
4896 .phy_id_mask = MICREL_PHY_ID_MASK,
4897 .name = "Microchip INDY Gigabit Quad PHY",
4898 .flags = PHY_POLL_CABLE_TEST,
4899 .config_init = lan8814_config_init,
4900 .driver_data = &lan8814_type,
4901 .probe = lan8814_probe,
4902 .soft_reset = genphy_soft_reset,
4903 .read_status = ksz9031_read_status,
4904 .get_sset_count = kszphy_get_sset_count,
4905 .get_strings = kszphy_get_strings,
4906 .get_stats = kszphy_get_stats,
4907 .suspend = genphy_suspend,
4908 .resume = kszphy_resume,
4909 .config_intr = lan8814_config_intr,
4910 .handle_interrupt = lan8814_handle_interrupt,
4911 .cable_test_start = lan8814_cable_test_start,
4912 .cable_test_get_status = ksz886x_cable_test_get_status,
4913 }, {
4914 .phy_id = PHY_ID_LAN8804,
4915 .phy_id_mask = MICREL_PHY_ID_MASK,
4916 .name = "Microchip LAN966X Gigabit PHY",
4917 .config_init = lan8804_config_init,
4918 .driver_data = &ksz9021_type,
4919 .probe = kszphy_probe,
4920 .soft_reset = genphy_soft_reset,
4921 .read_status = ksz9031_read_status,
4922 .get_sset_count = kszphy_get_sset_count,
4923 .get_strings = kszphy_get_strings,
4924 .get_stats = kszphy_get_stats,
4925 .suspend = genphy_suspend,
4926 .resume = kszphy_resume,
4927 .config_intr = lan8804_config_intr,
4928 .handle_interrupt = lan8804_handle_interrupt,
4929 }, {
4930 .phy_id = PHY_ID_LAN8841,
4931 .phy_id_mask = MICREL_PHY_ID_MASK,
4932 .name = "Microchip LAN8841 Gigabit PHY",
4933 .flags = PHY_POLL_CABLE_TEST,
4934 .driver_data = &lan8841_type,
4935 .config_init = lan8841_config_init,
4936 .probe = lan8841_probe,
4937 .soft_reset = genphy_soft_reset,
4938 .config_intr = lan8841_config_intr,
4939 .handle_interrupt = lan8841_handle_interrupt,
4940 .get_sset_count = kszphy_get_sset_count,
4941 .get_strings = kszphy_get_strings,
4942 .get_stats = kszphy_get_stats,
4943 .suspend = lan8841_suspend,
4944 .resume = genphy_resume,
4945 .cable_test_start = lan8814_cable_test_start,
4946 .cable_test_get_status = ksz886x_cable_test_get_status,
4947 }, {
4948 .phy_id = PHY_ID_KSZ9131,
4949 .phy_id_mask = MICREL_PHY_ID_MASK,
4950 .name = "Microchip KSZ9131 Gigabit PHY",
4951 /* PHY_GBIT_FEATURES */
4952 .flags = PHY_POLL_CABLE_TEST,
4953 .driver_data = &ksz9131_type,
4954 .probe = kszphy_probe,
4955 .soft_reset = genphy_soft_reset,
4956 .config_init = ksz9131_config_init,
4957 .config_intr = kszphy_config_intr,
4958 .config_aneg = ksz9131_config_aneg,
4959 .read_status = ksz9131_read_status,
4960 .handle_interrupt = kszphy_handle_interrupt,
4961 .get_sset_count = kszphy_get_sset_count,
4962 .get_strings = kszphy_get_strings,
4963 .get_stats = kszphy_get_stats,
4964 .suspend = kszphy_suspend,
4965 .resume = kszphy_resume,
4966 .cable_test_start = ksz9x31_cable_test_start,
4967 .cable_test_get_status = ksz9x31_cable_test_get_status,
4968 .get_features = ksz9477_get_features,
4969 }, {
4970 .phy_id = PHY_ID_KSZ8873MLL,
4971 .phy_id_mask = MICREL_PHY_ID_MASK,
4972 .name = "Micrel KSZ8873MLL Switch",
4973 /* PHY_BASIC_FEATURES */
4974 .config_init = kszphy_config_init,
4975 .config_aneg = ksz8873mll_config_aneg,
4976 .read_status = ksz8873mll_read_status,
4977 .suspend = genphy_suspend,
4978 .resume = genphy_resume,
4979 }, {
4980 .phy_id = PHY_ID_KSZ886X,
4981 .phy_id_mask = MICREL_PHY_ID_MASK,
4982 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4983 .driver_data = &ksz886x_type,
4984 /* PHY_BASIC_FEATURES */
4985 .flags = PHY_POLL_CABLE_TEST,
4986 .config_init = kszphy_config_init,
4987 .config_aneg = ksz886x_config_aneg,
4988 .read_status = ksz886x_read_status,
4989 .suspend = genphy_suspend,
4990 .resume = genphy_resume,
4991 .cable_test_start = ksz886x_cable_test_start,
4992 .cable_test_get_status = ksz886x_cable_test_get_status,
4993 }, {
4994 .name = "Micrel KSZ87XX Switch",
4995 /* PHY_BASIC_FEATURES */
4996 .config_init = kszphy_config_init,
4997 .match_phy_device = ksz8795_match_phy_device,
4998 .suspend = genphy_suspend,
4999 .resume = genphy_resume,
5000 }, {
5001 .phy_id = PHY_ID_KSZ9477,
5002 .phy_id_mask = MICREL_PHY_ID_MASK,
5003 .name = "Microchip KSZ9477",
5004 /* PHY_GBIT_FEATURES */
5005 .config_init = ksz9477_config_init,
5006 .config_intr = kszphy_config_intr,
5007 .handle_interrupt = kszphy_handle_interrupt,
5008 .suspend = genphy_suspend,
5009 .resume = ksz9477_resume,
5010 .get_features = ksz9477_get_features,
5011 } };
5012
5013 module_phy_driver(ksphy_driver);
5014
5015 MODULE_DESCRIPTION("Micrel PHY driver");
5016 MODULE_AUTHOR("David J. Choi");
5017 MODULE_LICENSE("GPL");
5018
5019 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
5020 { PHY_ID_KSZ9021, 0x000ffffe },
5021 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
5022 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
5023 { PHY_ID_KSZ8001, 0x00fffffc },
5024 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
5025 { PHY_ID_KSZ8021, 0x00ffffff },
5026 { PHY_ID_KSZ8031, 0x00ffffff },
5027 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
5028 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
5029 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
5030 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
5031 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
5032 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
5033 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
5034 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
5035 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
5036 { }
5037 };
5038
5039 MODULE_DEVICE_TABLE(mdio, micrel_tbl);
5040