1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2015-2016 Marvell International Ltd.
67 	/*-----------------------------------------------------------*/
144 	for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {  in comphy_poll_reg()
165 static int comphy_pcie_power_up(u32 speed, u32 invert)  in comphy_pcie_power_up()  argument
226 	 * 10. Check the Polarity invert bit  in comphy_pcie_power_up()
228 	if (invert & PHY_POLARITY_TXD_INVERT)  in comphy_pcie_power_up()
231 	if (invert & PHY_POLARITY_RXD_INVERT)  in comphy_pcie_power_up()
286 	 * 1. Select 40-bit data width width  in comphy_sata_power_up()
312 	 * 5. Set vendor-specific configuration (??)  in comphy_sata_power_up()
361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)  in comphy_usb3_power_up()  argument
380 	/* set PRD_TXDEEMPH (3.5db de-emph) */  in comphy_usb3_power_up()
387 	 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db  in comphy_usb3_power_up()
406 	/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */  in comphy_usb3_power_up()
445 	 * 7. Set 20-bit data width  in comphy_usb3_power_up()
456 	 * 9. Check the Polarity invert bit  in comphy_usb3_power_up()
458 	if (invert & PHY_POLARITY_TXD_INVERT)  in comphy_usb3_power_up()
461 	if (invert & PHY_POLARITY_RXD_INVERT)  in comphy_usb3_power_up()
697 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)  in comphy_sgmii_power_up()  argument
711 	 * 2. Reset PHY by setting PHY input port PIN_RESET=1.  in comphy_sgmii_power_up()
712 	 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep  in comphy_sgmii_power_up()
714 	 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.  in comphy_sgmii_power_up()
805 	 *     group to get the related GEN table during real chip bring-up.  in comphy_sgmii_power_up()
811 	debug("Running C-DPI phy init %s mode\n",  in comphy_sgmii_power_up()
828 	 * 18. Check the PHY Polarity invert bit  in comphy_sgmii_power_up()
830 	if (invert & PHY_POLARITY_TXD_INVERT)  in comphy_sgmii_power_up()
833 	if (invert & PHY_POLARITY_RXD_INVERT)  in comphy_sgmii_power_up()
837 	 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1  in comphy_sgmii_power_up()
858 	 * 21. Set COMPHY input port PIN_TX_IDLE=0  in comphy_sgmii_power_up()
892 	const void *blob = gd->fdt_blob;  in comphy_dedicated_phys_init()
903 				blob, -1, "marvell,armada3700-ehci");  in comphy_dedicated_phys_init()
906 				blob, -1, "marvell,armada3700-xhci");  in comphy_dedicated_phys_init()
925 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
926 					     "marvell,armada-3700-ahci");  in comphy_dedicated_phys_init()
941 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
942 					     "marvell,armada-8k-sdhci");  in comphy_dedicated_phys_init()
945 			blob, -1, "marvell,armada-3700-sdhci");  in comphy_dedicated_phys_init()
969 	u32 comphy_max_count = chip_cfg->comphy_lanes_count;  in comphy_a3700_init()
975 	chip_cfg->mux_data = a3700_comphy_mux_data;  in comphy_a3700_init()
981 		debug("Serdes type = 0x%x invert=%d\n",  in comphy_a3700_init()
982 		      comphy_map->type, comphy_map->invert);  in comphy_a3700_init()
984 		switch (comphy_map->type) {  in comphy_a3700_init()
990 			ret = comphy_pcie_power_up(comphy_map->speed,  in comphy_a3700_init()
991 						   comphy_map->invert);  in comphy_a3700_init()
997 						   comphy_map->type,  in comphy_a3700_init()
998 						   comphy_map->speed,  in comphy_a3700_init()
999 						   comphy_map->invert);  in comphy_a3700_init()
1004 			ret = comphy_sgmii_power_up(lane, comphy_map->speed,  in comphy_a3700_init()
1005 						    comphy_map->invert);  in comphy_a3700_init()
1015 			printf("PLL is not locked - Failed to initialize lane %d\n",  in comphy_a3700_init()