1 // SPDX-License-Identifier: GPL-2.0+
8  *   - drivers/pci/pcie_imx.c
9  *   - drivers/pci/pci_mvebu.c
10  *   - drivers/pci/pcie_xilinx.c
17 #include <asm-generic/gpio.h>
21 /* PCI Config space registers */
97  * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
99  * @ctrl_base: The base address of the register space
100  * @cfg_base: The base address of the configuration space
101  * @cfg_size: The size of the configuration space which is needed
104  *               first_busno stores the bus number of the PCIe root-port
132  * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
146 	       pcie->ctrl_base + PCIE_ATU_VIEWPORT);  in pcie_dw_prog_outbound_atu()
147 	writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);  in pcie_dw_prog_outbound_atu()
148 	writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);  in pcie_dw_prog_outbound_atu()
149 	writel(lower_32_bits(cpu_addr + size - 1),  in pcie_dw_prog_outbound_atu()
150 	       pcie->ctrl_base + PCIE_ATU_LIMIT);  in pcie_dw_prog_outbound_atu()
152 	       pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);  in pcie_dw_prog_outbound_atu()
154 	       pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);  in pcie_dw_prog_outbound_atu()
155 	writel(type, pcie->ctrl_base + PCIE_ATU_CR1);  in pcie_dw_prog_outbound_atu()
156 	writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);  in pcie_dw_prog_outbound_atu()
160  * set_cfg_address() - Configure the PCIe controller config space access
164  * @where: Offset in the configuration space
166  * Configures the PCIe controller to access the configuration space of
170  * Return: Address that can be used to access the configation space
180 	 * Region #0 is used for Outbound CFG space access.  in set_cfg_address()
185 	if (PCI_BUS(d) == (pcie->first_busno + 1))  in set_cfg_address()
192 	if (PCI_BUS(d) == pcie->first_busno) {  in set_cfg_address()
193 		/* Accessing root port configuration space. */  in set_cfg_address()
194 		va_address = (uintptr_t)pcie->ctrl_base;  in set_cfg_address()
196 		d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);  in set_cfg_address()
198 					  atu_type, (u64)pcie->cfg_base,  in set_cfg_address()
199 					  d << 8, pcie->cfg_size);  in set_cfg_address()
200 		va_address = (uintptr_t)pcie->cfg_base;  in set_cfg_address()
209  * pcie_dw_addr_valid() - Check for valid bus address
229  * pcie_dw_mvebu_read_config() - Read from configuration space
233  * @offset: The offset into the device's configuration space
237  * Read a value of size @size from offset @offset within the configuration
238  * space of the device identified by the bus, device & function numbers in @bdf
254 	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {  in pcie_dw_mvebu_read_config()
255 		debug("- out of range\n");  in pcie_dw_mvebu_read_config()
268 				  PCIE_ATU_TYPE_IO, pcie->io.phys_start,  in pcie_dw_mvebu_read_config()
269 				  pcie->io.bus_start, pcie->io.size);  in pcie_dw_mvebu_read_config()
275  * pcie_dw_mvebu_write_config() - Write to configuration space
279  * @offset: The offset into the device's configuration space
284  * configuration space of the device identified by the bus, device & function
301 	if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {  in pcie_dw_mvebu_write_config()
302 		debug("- out of range\n");  in pcie_dw_mvebu_write_config()
313 				  PCIE_ATU_TYPE_IO, pcie->io.phys_start,  in pcie_dw_mvebu_write_config()
314 				  pcie->io.bus_start, pcie->io.size);  in pcie_dw_mvebu_write_config()
320  * pcie_dw_configure() - Configure link capabilities and speed
344  * is_link_up() - Return the link state
363  * wait_link_up() - Wait for the link to come up
383  * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
396 		/* Disable LTSSM state machine to enable configuration */  in pcie_dw_mvebu_pcie_link_up()
413 		/* Configuration done. Start LTSSM */  in pcie_dw_mvebu_pcie_link_up()
432  * pcie_dw_set_host_bars() - Configure the host BARs
441 	u32 size = gd->ram_size;  in pcie_dw_set_host_bars()
452 		printf("Warning: PCIe BARs can't map all DRAM space\n");  in pcie_dw_set_host_bars()
460 	reg = ((size >> 20) - 1) << 12;  in pcie_dw_set_host_bars()
465  * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
472  * Return: 0 on success, else -ENODEV
482 	gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,  in pcie_dw_mvebu_probe()
485 	 * Issue reset to add-in card trough the dedicated GPIO.  in pcie_dw_mvebu_probe()
494 		dm_gpio_set_value(&reset_gpio, 0); /* de-assert */  in pcie_dw_mvebu_probe()
501 	pcie->first_busno = dev->seq;  in pcie_dw_mvebu_probe()
504 	if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {  in pcie_dw_mvebu_probe()
505 		printf("PCIE-%d: Link down\n", dev->seq);  in pcie_dw_mvebu_probe()
507 		printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,  in pcie_dw_mvebu_probe()
508 		       pcie_dw_get_link_speed(pcie->ctrl_base),  in pcie_dw_mvebu_probe()
509 		       pcie_dw_get_link_width(pcie->ctrl_base),  in pcie_dw_mvebu_probe()
510 		       hose->first_busno);  in pcie_dw_mvebu_probe()
514 	pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */  in pcie_dw_mvebu_probe()
515 	pcie->io.bus_start  = hose->regions[0].bus_start;  /* IO_bus_addr */  in pcie_dw_mvebu_probe()
516 	pcie->io.size	    = hose->regions[0].size;	   /* IO size */  in pcie_dw_mvebu_probe()
518 	pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */  in pcie_dw_mvebu_probe()
519 	pcie->mem.bus_start  = hose->regions[1].bus_start;  /* MEM_bus_addr */  in pcie_dw_mvebu_probe()
520 	pcie->mem.size	     = hose->regions[1].size;	    /* MEM size */  in pcie_dw_mvebu_probe()
523 				  PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,  in pcie_dw_mvebu_probe()
524 				  pcie->mem.bus_start, pcie->mem.size);  in pcie_dw_mvebu_probe()
527 	clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,  in pcie_dw_mvebu_probe()
530 	pcie_dw_set_host_bars(pcie->ctrl_base);  in pcie_dw_mvebu_probe()
536  * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
544  * Return: 0 on success, else -EINVAL
551 	pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);  in pcie_dw_mvebu_ofdata_to_platdata()
552 	if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)  in pcie_dw_mvebu_ofdata_to_platdata()
553 		return -EINVAL;  in pcie_dw_mvebu_ofdata_to_platdata()
555 	/* Get the config space base address and size */  in pcie_dw_mvebu_ofdata_to_platdata()
556 	pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,  in pcie_dw_mvebu_ofdata_to_platdata()
557 							 &pcie->cfg_size);  in pcie_dw_mvebu_ofdata_to_platdata()
558 	if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)  in pcie_dw_mvebu_ofdata_to_platdata()
559 		return -EINVAL;  in pcie_dw_mvebu_ofdata_to_platdata()
570 	{ .compatible = "marvell,armada8k-pcie" },