drivers/net/lpc32xx_eth.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * LPC32xx Ethernet MAC interface driver
6  * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
76 /* Ethernet MAC interface registers (see Table 283) */
78 	/* MAC registers - 0x3106_0000 to 0x3106_01FC */
79 	u32 mac1;		/* MAC configuration register 1 */
80 	u32 mac2;		/* MAC configuration register 2 */
81 	u32 ipgt;		/* Back-to-back Inter-Packet Gap reg. */
82 	u32 ipgr;		/* Non-back-to-back IPG register */
89 	u32 madr;		/* MII management address register */
94 	u32 sa0;		/* Station address register 0 */
95 	u32 sa1;		/* Station address register 1 */
96 	u32 sa2;		/* Station address register 2 */
119 	/* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
127 	/* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
222  * mii_reg_read - miiphy_read callback function.
230 	struct eth_device *dev = eth_get_dev_by_name(bus->name);  in mii_reg_read()
232 	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;  in mii_reg_read()
238 		printf("%s:%u: Invalid PHY address %d\n",  in mii_reg_read()
240 		return -EFAULT;  in mii_reg_read()
245 		return -EFAULT;  in mii_reg_read()
248 	/* write the phy and reg addressse into the MII address reg */  in mii_reg_read()
250 	       &regs->madr);  in mii_reg_read()
253 	writel(1, &regs->mcmd);  in mii_reg_read()
259 		mind_reg = readl(&regs->mind);  in mii_reg_read()
260 		if (--timeout == 0)  in mii_reg_read()
265 	writel(0, &regs->mcmd);  in mii_reg_read()
269 		return -EFAULT;  in mii_reg_read()
272 	data = (u16) readl(&regs->mrdd);  in mii_reg_read()
281  * mii_reg_write - imiiphy_write callback function.
283  * Returns 0 if write succeed, -EINVAL on bad parameters
284  * -ETIME on timeout
289 	struct eth_device *dev = eth_get_dev_by_name(bus->name);  in mii_reg_write()
291 	struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;  in mii_reg_write()
297 		printf("%s:%u: Invalid PHY address %d\n",  in mii_reg_write()
299 		return -EFAULT;  in mii_reg_write()
304 		return -EFAULT;  in mii_reg_write()
307 	/* write the phy and reg addressse into the MII address reg */  in mii_reg_write()
309 	       &regs->madr);  in mii_reg_write()
312 	writel(data, &regs->mwtd);  in mii_reg_write()
318 		mind_reg = readl(&regs->mind);  in mii_reg_write()
319 		if (--timeout == 0)  in mii_reg_write()
326 		return -EFAULT;  in mii_reg_write()
337  * Provide default Ethernet buffers base address if target did not.
359 	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;  in lpc32xx_eth_send()
360 	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;  in lpc32xx_eth_send()
365 	while ((readl(&regs->status) & STATUS_TXSTATUS) &&  in lpc32xx_eth_send()
366 	       (readl(&regs->txconsumeindex)  in lpc32xx_eth_send()
367 	       == readl(&regs->txproduceindex))) {  in lpc32xx_eth_send()
368 		if (timeout-- == 0)  in lpc32xx_eth_send()
369 			return -1;  in lpc32xx_eth_send()
373 	tx_index = readl(&regs->txproduceindex);  in lpc32xx_eth_send()
376 	writel((u32)dataptr, &bufs->tx_desc[tx_index].packet);  in lpc32xx_eth_send()
377 	writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),  in lpc32xx_eth_send()
378 	       &bufs->tx_desc[tx_index].control);  in lpc32xx_eth_send()
379 	writel(0, &bufs->tx_stat[tx_index].statusinfo);  in lpc32xx_eth_send()
383 	writel(tx_index, &regs->txproduceindex);  in lpc32xx_eth_send()
395 	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;  in lpc32xx_eth_recv()
396 	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;  in lpc32xx_eth_recv()
401 	while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {  in lpc32xx_eth_recv()
402 		if (timeout-- == 0)  in lpc32xx_eth_recv()
403 			return -1;  in lpc32xx_eth_recv()
407 	rx_index = readl(&regs->rxconsumeindex);  in lpc32xx_eth_recv()
410 	if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {  in lpc32xx_eth_recv()
412 			&(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),  in lpc32xx_eth_recv()
413 			(bufs->rx_stat[rx_index].statusinfo  in lpc32xx_eth_recv()
419 	writel(rx_index, &regs->rxconsumeindex);  in lpc32xx_eth_recv()
429 	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;  in lpc32xx_eth_write_hwaddr()
431 	/* Save station address */  in lpc32xx_eth_write_hwaddr()
432 	writel((unsigned long) (dev->enetaddr[0] |  in lpc32xx_eth_write_hwaddr()
433 		(dev->enetaddr[1] << 8)), &regs->sa2);  in lpc32xx_eth_write_hwaddr()
434 	writel((unsigned long) (dev->enetaddr[2] |  in lpc32xx_eth_write_hwaddr()
435 		(dev->enetaddr[3] << 8)), &regs->sa1);  in lpc32xx_eth_write_hwaddr()
436 	writel((unsigned long) (dev->enetaddr[4] |  in lpc32xx_eth_write_hwaddr()
437 		(dev->enetaddr[5] << 8)), &regs->sa0);  in lpc32xx_eth_write_hwaddr()
446 	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;  in lpc32xx_eth_init()
447 	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;  in lpc32xx_eth_init()
450 	/* Initial MAC initialization */  in lpc32xx_eth_init()
451 	writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);  in lpc32xx_eth_init()
452 	writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);  in lpc32xx_eth_init()
453 	writel(PKTSIZE_ALIGN, &regs->maxf);  in lpc32xx_eth_init()
456 	writel(0x370F, &regs->clrt);  in lpc32xx_eth_init()
458 	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */  in lpc32xx_eth_init()
459 	writel(0x0012, &regs->ipgr);  in lpc32xx_eth_init()
462 	if (lpc32xx_eth_device->phy_rmii)  in lpc32xx_eth_init()
463 		writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);  in lpc32xx_eth_init()
465 		writel(COMMAND_PASSRUNTFRAME, &regs->command);  in lpc32xx_eth_init()
468 	if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {  in lpc32xx_eth_init()
469 		setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);  in lpc32xx_eth_init()
470 		setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);  in lpc32xx_eth_init()
471 		writel(0x15, &regs->ipgt);  in lpc32xx_eth_init()
473 		writel(0x12, &regs->ipgt);  in lpc32xx_eth_init()
477 	if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)  in lpc32xx_eth_init()
478 		writel(SUPP_SPEED, &regs->supp);  in lpc32xx_eth_init()
480 		writel(0, &regs->supp);  in lpc32xx_eth_init()
482 	/* Save station address */  in lpc32xx_eth_init()
483 	writel((unsigned long) (dev->enetaddr[0] |  in lpc32xx_eth_init()
484 		(dev->enetaddr[1] << 8)), &regs->sa2);  in lpc32xx_eth_init()
485 	writel((unsigned long) (dev->enetaddr[2] |  in lpc32xx_eth_init()
486 		(dev->enetaddr[3] << 8)), &regs->sa1);  in lpc32xx_eth_init()
487 	writel((unsigned long) (dev->enetaddr[4] |  in lpc32xx_eth_init()
488 		(dev->enetaddr[5] << 8)), &regs->sa0);  in lpc32xx_eth_init()
492 		bufs->tx_desc[index].control = 0;  in lpc32xx_eth_init()
493 		bufs->tx_stat[index].statusinfo = 0;  in lpc32xx_eth_init()
495 	writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);  in lpc32xx_eth_init()
496 	writel((u32)(&bufs->tx_stat), &regs->txstatus);  in lpc32xx_eth_init()
497 	writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);  in lpc32xx_eth_init()
501 		bufs->rx_desc[index].packet =  in lpc32xx_eth_init()
502 			(u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);  in lpc32xx_eth_init()
503 		bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;  in lpc32xx_eth_init()
504 		bufs->rx_stat[index].statusinfo = 0;  in lpc32xx_eth_init()
505 		bufs->rx_stat[index].statushashcrc = 0;  in lpc32xx_eth_init()
507 	writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);  in lpc32xx_eth_init()
508 	writel((u32)(&bufs->rx_stat), &regs->rxstatus);  in lpc32xx_eth_init()
509 	writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);  in lpc32xx_eth_init()
511 	/* Enable broadcast and matching address packets */  in lpc32xx_eth_init()
513 		RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);  in lpc32xx_eth_init()
516 	writel(0xFFFF, &regs->intclear);  in lpc32xx_eth_init()
517 	writel(0, &regs->intenable);  in lpc32xx_eth_init()
519 	/* Enable receive and transmit mode of MAC ethernet core */  in lpc32xx_eth_init()
520 	setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);  in lpc32xx_eth_init()
521 	setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);  in lpc32xx_eth_init()
539 	struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;  in lpc32xx_eth_halt()
541 	/* Reset all MAC logic */  in lpc32xx_eth_halt()
542 	writel(MAC1_RESETS, &regs->mac1);  in lpc32xx_eth_halt()
543 	writel(COMMAND_RESETS, &regs->command);  in lpc32xx_eth_halt()
562 		return -ENOMEM;  in lpc32xx_eth_phylib_init()
564 	bus->read = mii_reg_read;  in lpc32xx_eth_phylib_init()
565 	bus->write = mii_reg_write;  in lpc32xx_eth_phylib_init()
566 	strcpy(bus->name, dev->name);  in lpc32xx_eth_phylib_init()
572 		return -ENOMEM;  in lpc32xx_eth_phylib_init()
575 	if (lpc32xx_eth_device->phy_rmii)  in lpc32xx_eth_phylib_init()
582 		return -ENODEV;  in lpc32xx_eth_phylib_init()
601 	writel(MCFG_RESET_MII_MGMT, &regs->mcfg);  in lpc32xx_eth_initialize()
602 	writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);  in lpc32xx_eth_initialize()
604 	/* Reset all MAC logic */  in lpc32xx_eth_initialize()
605 	writel(MAC1_RESETS, &regs->mac1);  in lpc32xx_eth_initialize()
606 	writel(COMMAND_RESETS, &regs->command);  in lpc32xx_eth_initialize()
611 	/* must be less than sizeof(dev->name) */  in lpc32xx_eth_initialize()
612 	strcpy(dev->name, "eth0");  in lpc32xx_eth_initialize()
614 	dev->init = (void *)lpc32xx_eth_init;  in lpc32xx_eth_initialize()
615 	dev->halt = (void *)lpc32xx_eth_halt;  in lpc32xx_eth_initialize()
616 	dev->send = (void *)lpc32xx_eth_send;  in lpc32xx_eth_initialize()
617 	dev->recv = (void *)lpc32xx_eth_recv;  in lpc32xx_eth_initialize()
618 	dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;  in lpc32xx_eth_initialize()
621 	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);  in lpc32xx_eth_initialize()
632 		return -ENOMEM;  in lpc32xx_eth_initialize()
633 	strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);  in lpc32xx_eth_initialize()
634 	mdiodev->read = mii_reg_read;  in lpc32xx_eth_initialize()
635 	mdiodev->write = mii_reg_write;  in lpc32xx_eth_initialize()