Lines Matching +full:static +full:- +full:beta
1 // SPDX-License-Identifier: GPL-2.0
21 static void sdram_mmr_init(void);
22 static u64 sdram_size_calc(void);
24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
44 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
46 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
48 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
51 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
53 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
57 static u32 ddr_config[] = {
58 /* Chip - Row - Bank - Column Style */
76 /* Chip - Bank - Row - Column Style */
94 static int match_ddr_conf(u32 ddr_conf) in match_ddr_conf()
105 static int emif_clear(void) in emif_clear()
113 static int emif_reset(void) in emif_reset()
131 return -EPERM; in emif_reset()
150 return -EPERM; in emif_reset()
162 static int ddr_setup(void) in ddr_setup()
169 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat, in ddr_setup()
180 return -EPERM; in ddr_setup()
183 static int sdram_is_ecc_enabled(void) in sdram_is_ecc_enabled()
185 return !!(readl(&socfpga_ecc_hmc_base->eccctrl) & in sdram_is_ecc_enabled()
190 static void sdram_init_ecc_bits(u32 size) in sdram_init_ecc_bits()
195 gd->arch.tlb_addr = 0x4000; in sdram_init_ecc_bits()
196 gd->arch.tlb_size = PGTABLE_SIZE; in sdram_init_ecc_bits()
201 memset((void *)0x8000, 0, size - 0x8000); in sdram_init_ecc_bits()
208 static int sdram_startup(void) in sdram_startup()
217 static u64 sdram_size_calc(void) in sdram_size_calc()
219 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); in sdram_size_calc()
235 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & in sdram_size_calc()
244 static void sdram_mmr_init(void) in sdram_mmr_init()
247 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); in sdram_mmr_init()
248 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); in sdram_mmr_init()
249 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); in sdram_mmr_init()
250 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); in sdram_mmr_init()
251 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); in sdram_mmr_init()
252 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); in sdram_mmr_init()
253 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); in sdram_mmr_init()
254 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); in sdram_mmr_init()
255 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); in sdram_mmr_init()
262 * bit[8] = 1 if user-mode OCT is present in sdram_mmr_init()
266 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, in sdram_mmr_init()
267 * 3=EAP, 4-6 are reserved) in sdram_mmr_init()
272 if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) { in sdram_mmr_init()
273 update_value = readl(&socfpga_io48_mmr_base->niosreserve0); in sdram_mmr_init()
275 &socfpga_ecc_hmc_base->ddrioctrl); in sdram_mmr_init()
278 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); in sdram_mmr_init()
300 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); in sdram_mmr_init()
304 * RDTOMISS = tRTP + tRP + tRCD - BL/2 in sdram_mmr_init()
306 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... in sdram_mmr_init()
309 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD in sdram_mmr_init()
359 caltim0_cfg_act_to_rdwr - in sdram_mmr_init()
362 io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) & in sdram_mmr_init()
364 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - in sdram_mmr_init()
383 &socfpga_noc_ddr_scheduler_base-> in sdram_mmr_init()
389 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); in sdram_mmr_init()
392 writel(((readl(&socfpga_io48_mmr_base->dramtiming0) & in sdram_mmr_init()
395 &socfpga_noc_ddr_scheduler_base-> in sdram_mmr_init()
408 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); in sdram_mmr_init()
420 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); in sdram_mmr_init()
424 setbits_le32(&socfpga_ecc_hmc_base->eccctrl, in sdram_mmr_init()
428 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, in sdram_mmr_init()
431 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, in sdram_mmr_init()
435 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, in sdram_mmr_init()
439 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, in sdram_mmr_init()
490 "l3-0",
496 "l3-1",
502 "l3-2",
508 "l3-3",
514 "l3-4",
520 "l3-5",
526 "l3-6",
532 "l3-7",
538 "fpga2sdram0-0",
545 "fpga2sdram0-1",
552 "fpga2sdram0-2",
559 "fpga2sdram0-3",
566 "fpga2sdram1-0",
573 "fpga2sdram1-1",
580 "fpga2sdram1-2",
587 "fpga2sdram1-3",
594 "fpga2sdram2-0",
601 "fpga2sdram2-1",
608 "fpga2sdram2-2",
615 "fpga2sdram2-3",
624 static int of_sdram_firewall_setup(const void *blob) in of_sdram_firewall_setup()
632 return -ENXIO; in of_sdram_firewall_setup()
636 return -ENXIO; in of_sdram_firewall_setup()
639 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); in of_sdram_firewall_setup()
640 writel(0, &socfpga_noc_fw_ddr_l3_base->enable); in of_sdram_firewall_setup()
672 return -EPERM; in ddr_calibration_sequence()
691 gd->ram_size = PHYS_SDRAM_1_SIZE; in ddr_calibration_sequence()
693 gd->ram_size = DDR_SIZE_2GB_HEX; in ddr_calibration_sequence()
695 gd->ram_size = (u32)size; in ddr_calibration_sequence()
700 if (of_sdram_firewall_setup(gd->fdt_blob)) in ddr_calibration_sequence()
704 sdram_init_ecc_bits(gd->ram_size); in ddr_calibration_sequence()