Lines Matching +full:base +full:- +full:64
1 // SPDX-License-Identifier: GPL-2.0-or-later
48 #define ASPEED_SHA384_DIGEST_SIZE 64
49 #define ASPEED_SHA512_DIGEST_SIZE 64
63 u8 digest[64]; /* Must be 8 byte aligned */
100 static phys_addr_t base; variable
114 if (ctx->block_size == 64) { in aspeed_ahash_fill_padding()
115 bits[0] = cpu_to_be64(ctx->digcnt[0] << 3); in aspeed_ahash_fill_padding()
116 index = (ctx->bufcnt + remainder) & 0x3f; in aspeed_ahash_fill_padding()
117 padlen = (index < 56) ? (56 - index) : ((64 + 56) - index); in aspeed_ahash_fill_padding()
118 *(ctx->buffer + ctx->bufcnt) = 0x80; in aspeed_ahash_fill_padding()
119 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen - 1); in aspeed_ahash_fill_padding()
120 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 8); in aspeed_ahash_fill_padding()
121 ctx->bufcnt += padlen + 8; in aspeed_ahash_fill_padding()
123 bits[1] = cpu_to_be64(ctx->digcnt[0] << 3); in aspeed_ahash_fill_padding()
124 bits[0] = cpu_to_be64(ctx->digcnt[1] << 3 | ctx->digcnt[0] >> 61); in aspeed_ahash_fill_padding()
125 index = (ctx->bufcnt + remainder) & 0x7f; in aspeed_ahash_fill_padding()
126 padlen = (index < 112) ? (112 - index) : ((128 + 112) - index); in aspeed_ahash_fill_padding()
127 *(ctx->buffer + ctx->bufcnt) = 0x80; in aspeed_ahash_fill_padding()
128 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen - 1); in aspeed_ahash_fill_padding()
129 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16); in aspeed_ahash_fill_padding()
130 ctx->bufcnt += padlen + 16; in aspeed_ahash_fill_padding()
136 if (readl(base + ASPEED_HACE_STS) & HACE_HASH_BUSY) { in hash_trigger()
138 return -EBUSY; in hash_trigger()
141 writel(HACE_HASH_ISR, base + ASPEED_HACE_STS); in hash_trigger()
143 writel((u32)ctx->sg, base + ASPEED_HACE_HASH_SRC); in hash_trigger()
144 writel((u32)ctx->digest, base + ASPEED_HACE_HASH_DIGEST_BUFF); in hash_trigger()
145 writel((u32)ctx->digest, base + ASPEED_HACE_HASH_KEY_BUFF); in hash_trigger()
146 writel(hash_len, base + ASPEED_HACE_HASH_DATA_LEN); in hash_trigger()
147 writel(ctx->method, base + ASPEED_HACE_HASH_CMD); in hash_trigger()
150 return aspeed_hace_wait_completion(base + ASPEED_HACE_STS, in hash_trigger()
166 if (!strcmp(algo->name, "sha1")) { in hw_sha_init()
168 block_size = 64; in hw_sha_init()
169 memcpy(ctx->digest, sha1_iv, 32); in hw_sha_init()
170 } else if (!strcmp(algo->name, "sha256")) { in hw_sha_init()
172 block_size = 64; in hw_sha_init()
173 memcpy(ctx->digest, sha256_iv, 32); in hw_sha_init()
174 } else if (!strcmp(algo->name, "sha384")) { in hw_sha_init()
177 memcpy(ctx->digest, sha384_iv, 64); in hw_sha_init()
178 } else if (!strcmp(algo->name, "sha512")) { in hw_sha_init()
181 memcpy(ctx->digest, sha512_iv, 64); in hw_sha_init()
183 return -ENOTSUPP; in hw_sha_init()
188 return -ENOMEM; in hw_sha_init()
191 ctx->method = method; in hw_sha_init()
192 ctx->block_size = block_size; in hw_sha_init()
193 ctx->digest_size = algo->digest_size; in hw_sha_init()
194 ctx->bufcnt = 0; in hw_sha_init()
195 ctx->digcnt[0] = 0; in hw_sha_init()
196 ctx->digcnt[1] = 0; in hw_sha_init()
206 struct aspeed_sg *sg = ctx->sg; in hw_sha_update()
212 ctx->digcnt[0] += size; in hw_sha_update()
213 if (ctx->digcnt[0] < size) in hw_sha_update()
214 ctx->digcnt[1]++; in hw_sha_update()
216 if (ctx->bufcnt + size < ctx->block_size) { in hw_sha_update()
217 memcpy(ctx->buffer + ctx->bufcnt, buf, size); in hw_sha_update()
218 ctx->bufcnt += size; in hw_sha_update()
221 remainder = (size + ctx->bufcnt) % ctx->block_size; in hw_sha_update()
222 total_len = size + ctx->bufcnt - remainder; in hw_sha_update()
224 if (ctx->bufcnt != 0) { in hw_sha_update()
225 sg[0].addr = (u32)ctx->buffer; in hw_sha_update()
226 sg[0].len = ctx->bufcnt; in hw_sha_update()
227 if (total_len == ctx->bufcnt) in hw_sha_update()
232 if (total_len != ctx->bufcnt) { in hw_sha_update()
234 sg[i].len = (total_len - ctx->bufcnt) | HACE_SG_LAST; in hw_sha_update()
239 memcpy(ctx->buffer, buf + (total_len - ctx->bufcnt), remainder); in hw_sha_update()
240 ctx->bufcnt = remainder; in hw_sha_update()
242 ctx->bufcnt = 0; in hw_sha_update()
251 struct aspeed_sg *sg = ctx->sg; in hw_sha_finish()
254 if (size < ctx->digest_size) { in hw_sha_finish()
257 return -EINVAL; in hw_sha_finish()
261 sg[0].addr = (u32)ctx->buffer; in hw_sha_finish()
262 sg[0].len = ctx->bufcnt | HACE_SG_LAST; in hw_sha_finish()
264 rc = hash_trigger(ctx, ctx->bufcnt); in hw_sha_finish()
265 memcpy(dest_buf, ctx->digest, ctx->digest_size); in hw_sha_finish()
281 return -EINVAL; in sha_digest()
284 if (readl(base + ASPEED_HACE_STS) & HACE_HASH_BUSY) { in sha_digest()
286 return -EBUSY; in sha_digest()
294 return -ENOMEM; in sha_digest()
296 ctx->method = HASH_CMD_ACC_MODE | HACE_SHA_BE_EN | HACE_SG_EN; in sha_digest()
300 ctx->block_size = 64; in sha_digest()
301 ctx->digest_size = 20; in sha_digest()
302 ctx->method |= HACE_ALGO_SHA1; in sha_digest()
303 memcpy(ctx->digest, sha1_iv, 32); in sha_digest()
306 ctx->block_size = 64; in sha_digest()
307 ctx->digest_size = 32; in sha_digest()
308 ctx->method |= HACE_ALGO_SHA256; in sha_digest()
309 memcpy(ctx->digest, sha256_iv, 32); in sha_digest()
312 ctx->block_size = 128; in sha_digest()
313 ctx->digest_size = 64; in sha_digest()
314 ctx->method |= HACE_ALGO_SHA384; in sha_digest()
315 memcpy(ctx->digest, sha384_iv, 64); in sha_digest()
318 ctx->block_size = 128; in sha_digest()
319 ctx->digest_size = 64; in sha_digest()
320 ctx->method |= HACE_ALGO_SHA512; in sha_digest()
321 memcpy(ctx->digest, sha512_iv, 64); in sha_digest()
324 return -ENOTSUPP; in sha_digest()
327 ctx->digcnt[0] = length; in sha_digest()
328 ctx->digcnt[1] = 0; in sha_digest()
333 ctx->sg[0].addr = (u32)src; in sha_digest()
334 ctx->sg[0].len = length; in sha_digest()
335 ctx->sg[1].addr = (u32)ctx->buffer; in sha_digest()
336 ctx->sg[1].len = ctx->bufcnt | HACE_SG_LAST; in sha_digest()
338 ctx->sg[0].addr = (u32)ctx->buffer; in sha_digest()
339 ctx->sg[0].len = ctx->bufcnt | HACE_SG_LAST; in sha_digest()
342 ret = hash_trigger(ctx, length + ctx->bufcnt); in sha_digest()
343 memcpy(digest, ctx->digest, ctx->digest_size); in sha_digest()
394 ret = clk_get_by_index(dev, 0, &hace->clk); in aspeed_hace_probe()
396 debug("Can't get clock for %s: %d\n", dev->name, ret); in aspeed_hace_probe()
400 ret = clk_enable(&hace->clk); in aspeed_hace_probe()
407 base = devfdt_get_addr(dev); in aspeed_hace_probe()
416 clk_disable(&hace->clk); in aspeed_hace_remove()
422 { .compatible = "aspeed,ast2600-hace" },