|
Revision tags: v00.04.09, v00.04.08 |
|
| #
c9ece5db |
| 27-Oct-2021 |
Johnny Huang <johnny_huang@aspeedtech.com> |
crypto: Fix Aspeed HACE driver
clear bufcnt when buffer used
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Change-Id: I8bb6c99d2183f59fef5c659701f2871bf9a81551
|
|
Revision tags: v00.04.07 |
|
| #
ebf0f73f |
| 18-Aug-2021 |
Johnny Huang <johnny_huang@aspeedtech.com> |
crypto: Add Aspeed HACE acc mode support
rework the Aspeed HASH driver by using acc mode
Change-Id: I251092d4fd9b97ce33c980140e869a3486f19c21
|
|
Revision tags: v00.04.06, v00.04.05, v00.04.04, v00.04.03 |
|
| #
d7dcf1da |
| 29-Jul-2021 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
aspeed/hace: Add SHA384 support
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ib7322dcf0b383cf4766c77546c7b913e05536f48
|
| #
0fdcca14 |
| 29-Jul-2021 |
Joel Stanley <joel@jms.id.au> |
aspeed/hace: Reset when error occurs
Some hasing operations have been triggering an error state.
This can be reproduced on the u-boot command line:
hash sha512 83000128 3762a8
This completes, and
aspeed/hace: Reset when error occurs
Some hasing operations have been triggering an error state.
This can be reproduced on the u-boot command line:
hash sha512 83000128 3762a8
This completes, and the hash is correct. However HACE1C, the status
register, shows an error bit is set 0x00800000.
$ bitfield HACE1C 0x00800000 |grep 0x1
Hash input data buffer overflow: 0x1
The next operation is queued, and this never completes. The status
register shows 0x00c00001
$ bitfield HACE1C 0x00c00001 |grep 0x1
Hash input data buffer overflow: 0x1
Hash input rorate data overflow: 0x1
Hash engine busy: 0x1
A HACE reset will clear this state:
mw.l 0x1e6e2040 0x10
mw.l 0x1e6e2044 0x10
Adding code to do this if any error bits are set in the status register
is a workaround for the issue while further debugging is done.
Another workaround is to do an operation before running the problematic
operation. This sequence succeeds:
hash sha512 83000000 10
hash sha512 83000128 3762a8
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I4e078d7270513244c41824bc9e0867a29383cbbd
show more ...
|
|
Revision tags: v00.04.02, v00.04.01, v00.04.00 |
|
| #
e31caa5a |
| 03-May-2021 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
crypto: Add Aspeed HACE support
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ia4f95179c58dfb3ffb5bc20ddca9aef73083309c
|
| #
a570745a |
| 14-Jul-2021 |
Joel Stanley <joel@jms.id.au> |
aspeed/hace: Reset when error occurs
Some hasing operations have been triggering an error state.
This can be reproduced on the u-boot command line:
hash sha512 83000128 376
aspeed/hace: Reset when error occurs
Some hasing operations have been triggering an error state.
This can be reproduced on the u-boot command line:
hash sha512 83000128 3762a8
This completes, and the hash is correct. However HACE1C, the status
register, shows an error bit is set 0x00800000.
$ bitfield HACE1C 0x00800000 |grep 0x1
Hash input data buffer overflow: 0x1
The next operation is queued, and this never completes. The status
register shows 0x00c00001
$ bitfield HACE1C 0x00c00001 |grep 0x1
Hash input data buffer overflow: 0x1
Hash input rorate data overflow: 0x1
Hash engine busy: 0x1
A HACE reset will clear this state:
mw.l 0x1e6e2040 0x10
mw.l 0x1e6e2044 0x10
Adding code to do this if any error bits are set in the status register
is a workaround for the issue while further debugging is done.
Another workaround is to do an operation before running the problematic
operation. This sequence succeeds:
hash sha512 83000000 10
hash sha512 83000128 3762a8
Tested-by: Adriana Kobylak <anoo@us.ibm.com>
Link: https://lore.kernel.org/r/20210715045258.13912-1-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
| #
5ea2a312 |
| 13-Apr-2021 |
Joel Stanley <joel@jms.id.au> |
crypto: Add driver for Aspeed HACE
The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
uses it in a polling mode to perform hash calculations over buffers
placed
crypto: Add driver for Aspeed HACE
The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
uses it in a polling mode to perform hash calculations over buffers
placed in DRAM.
Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
| #
ee16ee61 |
| 13-Apr-2021 |
Joel Stanley <joel@jms.id.au> |
crypto: Add driver for Aspeed HACE
The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
uses it in a polling mode to perform hash calculations over buffers
placed
crypto: Add driver for Aspeed HACE
The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
uses it in a polling mode to perform hash calculations over buffers
placed in DRAM.
Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|