drivers/clk/mpc83xx_clk.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
8  * enum ratio - Description of a core clock ratio
34  * struct corecnf - Description for a core clock configuration
35  * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
36  * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
44  * Table with all valid Core CSB frequency ratio / VCO divider combinations as
79  * enum reg_type - Register to read a field from
89  * enum mode_type - Description of how to read a specific frequency value
92  *			       as a divider for the CSB clock to compute the
93  *			       frequency
95  *			       clock on or off
97  *			       as a multiplier for the CSB clock to compute the
98  *			       frequency
99  * @TYPE_SPECIAL:              The frequency is calculated in a non-standard way
109 /* Map of each clock index to its human-readable name */
112 	[MPC83XX_CLK_CSB] = "Coherent System Bus",
136  * struct clk_mode - Structure for clock mode descriiptions
150  * set_mode() - Build a clock mode description from data
151  * @mode: The clock mode description to be filled out
158  * Clock mode descriptions are a succinct description of how to read a specific
159  * clock's rate from the hardware; usually by reading a specific field of a
161  * for obtaining the clock rate.
165 	mode->low = low;  in set_mode()
166 	mode->high = high;  in set_mode()
167 	mode->type = type;  in set_mode()
171  * retrieve_mode() - Get the clock mode description for a specific clock
172  * @clk:      The identifier of the clock for which the clock description should
174  * @soc_type: The type of MPC83xx SoC for which the clock description should be
177  *	      clock
179  * Since some clock rate are stored in different places on different MPC83xx
180  * SoCs, the SoC type has to be supplied along with the clock's identifier.
182  * Return: 0 if OK, -ve on error
245 		/* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */  in retrieve_mode()
260 		debug("%s: Unknown clock type %d on soc type %d\n",  in retrieve_mode()
263 		return -EINVAL;  in retrieve_mode()
270  * get_spmr() - Read the SPMR (System PLL Mode Register)
273  * Return: The SPMR value as a 32-bit number.
277 	u32 res = in_be32(&im->clk.spmr);  in get_spmr()
283  * get_sccr() - Read the SCCR (System Clock Control Register)
286  * Return: The SCCR value as a 32-bit number.
290 	u32 res = in_be32(&im->clk.sccr);  in get_sccr()
296  * get_lcrr() - Read the LCRR (Clock Ratio Register)
299  * Return: The LCRR value as a 32-bit number.
303 	u32 res = in_be32(&im->im_lbc.lcrr);  in get_lcrr()
309  * get_pci_sync_in() - Read the PCI synchronization clock speed
312  * Return: The PCI synchronization clock speed value as a 32-bit number.
323  * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
326  * Return: The CSB clock speed value as a 32-bit number.
337  * spmr_field() - Read a specific SPMR field
341  * Return: The value of the bit field as a 32-bit number.
346 	uint shift = mask ? ffs(mask) - 1 : 0;  in spmr_field()
352  * sccr_field() - Read a specific SCCR field
356  * Return: The value of the bit field as a 32-bit number.
361 	uint shift = mask ? ffs(mask) - 1 : 0;  in sccr_field()
367  * lcrr_field() - Read a specific LCRR field
371  * Return: The value of the bit field as a 32-bit number.
376 	uint shift = mask ? ffs(mask) - 1 : 0;  in lcrr_field()