1 /* SPDX-License-Identifier: GPL-2.0+ */
8  * enum ratio - Description of a core clock ratio
34  * struct corecnf - Description for a core clock configuration
79  * enum reg_type - Register to read a field from
89  * enum mode_type - Description of how to read a specific frequency value
99  * @TYPE_SPECIAL:              The frequency is calculated in a non-standard way
109 /* Map of each clock index to its human-readable name */
136  * struct clk_mode - Structure for clock mode descriiptions
150  * set_mode() - Build a clock mode description from data
165 	mode->low = low;  in set_mode()
166 	mode->high = high;  in set_mode()
167 	mode->type = type;  in set_mode()
171  * retrieve_mode() - Get the clock mode description for a specific clock
182  * Return: 0 if OK, -ve on error
263 		return -EINVAL;  in retrieve_mode()
270  * get_spmr() - Read the SPMR (System PLL Mode Register)
271  * @im: Pointer to the MPC83xx main register map in question
273  * Return: The SPMR value as a 32-bit number.
275 static inline u32 get_spmr(immap_t *im)  in get_spmr()  argument
277 	u32 res = in_be32(&im->clk.spmr);  in get_spmr()
283  * get_sccr() - Read the SCCR (System Clock Control Register)
284  * @im: Pointer to the MPC83xx main register map in question
286  * Return: The SCCR value as a 32-bit number.
288 static inline u32 get_sccr(immap_t *im)  in get_sccr()  argument
290 	u32 res = in_be32(&im->clk.sccr);  in get_sccr()
296  * get_lcrr() - Read the LCRR (Clock Ratio Register)
297  * @im: Pointer to the MPC83xx main register map in question
299  * Return: The LCRR value as a 32-bit number.
301 static inline u32 get_lcrr(immap_t *im)  in get_lcrr()  argument
303 	u32 res = in_be32(&im->im_lbc.lcrr);  in get_lcrr()
309  * get_pci_sync_in() - Read the PCI synchronization clock speed
310  * @im: Pointer to the MPC83xx main register map in question
312  * Return: The PCI synchronization clock speed value as a 32-bit number.
314 static inline u32 get_pci_sync_in(immap_t *im)  in get_pci_sync_in()  argument
318 	clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;  in get_pci_sync_in()
323  * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
324  * @im: Pointer to the MPC83xx main register map in question
326  * Return: The CSB clock speed value as a 32-bit number.
328 static inline u32 get_csb_clk(immap_t *im)  in get_csb_clk()  argument
332 	spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;  in get_csb_clk()
337  * spmr_field() - Read a specific SPMR field
338  * @im:   Pointer to the MPC83xx main register map in question
341  * Return: The value of the bit field as a 32-bit number.
343 static inline uint spmr_field(immap_t *im, u32 mask)  in spmr_field()  argument
346 	uint shift = mask ? ffs(mask) - 1 : 0;  in spmr_field()
348 	return (get_spmr(im) & mask) >> shift;  in spmr_field()
352  * sccr_field() - Read a specific SCCR field
353  * @im:   Pointer to the MPC83xx main register map in question
356  * Return: The value of the bit field as a 32-bit number.
358 static inline uint sccr_field(immap_t *im, u32 mask)  in sccr_field()  argument
361 	uint shift = mask ? ffs(mask) - 1 : 0;  in sccr_field()
363 	return (get_sccr(im) & mask) >> shift;  in sccr_field()
367  * lcrr_field() - Read a specific LCRR field
368  * @im:   Pointer to the MPC83xx main register map in question
371  * Return: The value of the bit field as a 32-bit number.
373 static inline uint lcrr_field(immap_t *im, u32 mask)  in lcrr_field()  argument
376 	uint shift = mask ? ffs(mask) - 1 : 0;  in lcrr_field()
378 	return (get_lcrr(im) & mask) >> shift;  in lcrr_field()