Lines Matching +full:auto +full:- +full:boot
7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
33 { 0, 1, 0, "Disable Secure Boot" },
34 { 0, 1, 1, "Enable Secure Boot" },
35 { 1, 1, 0, "Disable boot from eMMC" },
36 { 1, 1, 1, "Enable boot from eMMC" },
37 { 2, 1, 0, "Disable Boot from debug SPI" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
67 { 19, 1, 0, "Boot from eMMC speed mode : normal" },
68 { 19, 1, 1, "Boot from eMMC speed mode : high" },
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
101 { 40, 1, 0, "Disable boot from uart5" },
102 { 40, 1, 1, "Enable boot from uart5" },
103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
105 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" },
106 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" },
107 { 43, 1, 0, "Disable boot SPI or eMMC ABR" },
108 { 43, 1, 1, "Enable boot SPI or eMMC ABR" },
109 { 44, 1, 0, "Boot SPI ABR Mode : dual" },
110 { 44, 1, 1, "Boot SPI ABR Mode : single" },
111 { 45, 3, 0, "Boot SPI flash size : 0MB" },
112 { 45, 3, 1, "Boot SPI flash size : 2MB" },
113 { 45, 3, 2, "Boot SPI flash size : 4MB" },
114 { 45, 3, 3, "Boot SPI flash size : 8MB" },
115 { 45, 3, 4, "Boot SPI flash size : 16MB" },
116 { 45, 3, 5, "Boot SPI flash size : 32MB" },
117 { 45, 3, 6, "Boot SPI flash size : 64MB" },
118 { 45, 3, 7, "Boot SPI flash size : 128MB" },
133 { 54, 1, 0, "Disable boot SPI auxiliary control pins" },
134 { 54, 1, 1, "Enable boot SPI auxiliary control pins" },
135 { 55, 2, 0, "Boot SPI CRTM size : 0KB" },
136 { 55, 2, 1, "Boot SPI CRTM size : 256KB" },
137 { 55, 2, 2, "Boot SPI CRTM size : 512KB" },
138 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" },
152 { 0, 1, 0, "Disable Secure Boot" },
153 { 0, 1, 1, "Enable Secure Boot" },
154 { 1, 1, 0, "Disable boot from eMMC" },
155 { 1, 1, 1, "Enable boot from eMMC" },
156 { 2, 1, 0, "Disable Boot from debug SPI" },
157 { 2, 1, 1, "Enable Boot from debug SPI" },
191 { 19, 1, 0, "Boot from eMMC speed mode : normal" },
192 { 19, 1, 1, "Boot from eMMC speed mode : high" },
198 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
230 { 40, 1, 0, "Disable boot from uart5" },
231 { 40, 1, 1, "Enable boot from uart5" },
232 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
233 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
234 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" },
235 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" },
236 { 43, 1, 0, "Disable boot SPI or eMMC ABR" },
237 { 43, 1, 1, "Enable boot SPI or eMMC ABR" },
238 { 44, 1, 0, "Boot SPI ABR Mode : dual" },
239 { 44, 1, 1, "Boot SPI ABR Mode : single" },
240 { 45, 3, 0, "Boot SPI flash size : 0MB" },
241 { 45, 3, 1, "Boot SPI flash size : 2MB" },
242 { 45, 3, 2, "Boot SPI flash size : 4MB" },
243 { 45, 3, 3, "Boot SPI flash size : 8MB" },
244 { 45, 3, 4, "Boot SPI flash size : 16MB" },
245 { 45, 3, 5, "Boot SPI flash size : 32MB" },
246 { 45, 3, 6, "Boot SPI flash size : 64MB" },
247 { 45, 3, 7, "Boot SPI flash size : 128MB" },
262 { 54, 1, 0, "Disable boot SPI auxiliary control pins" },
263 { 54, 1, 1, "Enable boot SPI auxiliary control pins" },
264 { 55, 2, 0, "Boot SPI CRTM size : 0KB" },
265 { 55, 2, 1, "Boot SPI CRTM size : 256KB" },
266 { 55, 2, 2, "Boot SPI CRTM size : 512KB" },
267 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" },
283 { 0, 1, 1, 0, "Disable Secure Boot" },
284 { 0, 1, 1, 1, "Enable Secure Boot" },
291 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" },
292 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" },
293 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" },
294 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" },
305 { 0, 15, 1, 0, "Enable Boot from Uart" },
306 { 0, 15, 1, 1, "Disable Boot from Uart" },
316 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" },
317 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" },
326 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" },
335 { 0, 1, 1, 0, "Disable Secure Boot" },
336 { 0, 1, 1, 1, "Enable Secure Boot" },
343 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" },
344 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" },
345 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" },
346 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" },
357 { 0, 15, 1, 0, "Enable Boot from Uart" },
358 { 0, 15, 1, 1, "Disable Boot from Uart" },
368 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" },
369 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" },
378 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" },
382 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" },
383 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" },
393 { 0, 1, 1, 0, "Disable Secure Boot" },
394 { 0, 1, 1, 1, "Enable Secure Boot" },
401 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" },
402 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" },
403 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" },
404 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" },
405 { 0, 9, 1, 0, "ROM code will dump boot messages" },
417 { 0, 15, 1, 0, "Enable Boot from Uart" },
418 { 0, 15, 1, 1, "Disable Boot from Uart" },
428 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" },
429 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" },
436 { 0, 30, 1, 0, "Boot from UART/VUART when normal boot is fail" },
437 { 0, 30, 1, 1, "Disable auto UART/VUART boot option" },
442 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" },
443 { 3, 16, 1, 0, "Boot from UART using: UART5" },
444 { 3, 16, 1, 1, "Boot from UART using: UART1" },
445 { 3, 17, 1, 0, "Enable Auto Boot from UART" },
446 { 3, 17, 1, 1, "Disable Auto Boot from UART" },
447 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" },
448 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" },
449 { 3, 19, 1, 0, "Enable Auto Boot from VUART2 over LPC" },
450 { 3, 19, 1, 1, "Disable Auto Boot from VUART2 over LPC" },
455 { 3, 30, 1, 0, "Do not erase signature data after secure boot check" },
456 { 3, 30, 1, 1, "Erase signature data after secure boot check" },
457 { 3, 31, 1, 0, "Do not erase RSA public key after secure boot check" },
458 { 3, 31, 1, 1, "Erase RSA public key after secure boot check" },
462 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" },
463 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" },
473 { 0, 1, 1, 0, "Disable Secure Boot" },
474 { 0, 1, 1, 1, "Enable Secure Boot" },
481 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" },
482 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" },
483 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" },
484 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" },
485 { 0, 9, 1, 0, "ROM code will dump boot messages" },
497 { 0, 15, 1, 0, "Enable Boot from Uart" },
498 { 0, 15, 1, 1, "Disable Boot from Uart" },
508 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" },
509 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" },
516 { 0, 30, 1, 0, "Boot from UART/VUART when normal boot is fail" },
517 { 0, 30, 1, 1, "Disable auto UART/VUART boot option" },
522 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" },
523 { 3, 16, 1, 0, "Boot from UART using: UART5" },
524 { 3, 16, 1, 1, "Boot from UART using: UART1" },
525 { 3, 17, 1, 0, "Enable Auto Boot from UART" },
526 { 3, 17, 1, 1, "Disable Auto Boot from UART" },
527 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" },
528 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" },
529 { 3, 19, 1, 0, "Enable Auto Boot from VUART2 over LPC" },
530 { 3, 19, 1, 1, "Disable Auto Boot from VUART2 over LPC" },
535 { 3, 30, 1, 0, "Do not erase signature data after secure boot check" },
536 { 3, 30, 1, 1, "Erase signature data after secure boot check" },
537 { 3, 31, 1, 0, "Do not erase RSA public key after secure boot check" },
538 { 3, 31, 1, 1, "Erase RSA public key after secure boot check" },
542 { 7, 0, 15, OTP_REG_VALUE, "SCU0C8[14:0] auto setting : 0x%x" },
545 { 7, 16, 15, OTP_REG_VALUE, "SCU0D8[14:0] auto setting : 0x%x" },
553 { 0, 1, "Disable ARM CA7 CPU boot (TXD5)" },
555 { 2, 1, "Enable boot from eMMC" },
556 { 3, 1, "Boot from debug SPI" },
569 { 20, 1, "Boot from eMMC speed mode" },
578 { 31, 1, "Enable boot SPI auxiliary control pins(mirror)" },
587 { 40, 1, "Enable boot from uart5" },
588 { 41, 1, "Enable boot SPI 3B address mode auto-clear" },
589 { 42, 1, "Enable SPI 3B/4B address mode auto detection" },
590 { 43, 1, "Enable boot SPI or eMMC ABR" },
591 { 44, 1, "Boot SPI ABR Mode" },
592 { 45, 3, "Boot SPI flash size" },
597 { 54, 1, "Enable boot SPI auxiliary control pins" },
598 { 55, 2, "Boot SPI CRTM size" },