90 						    PAD_CTL_DSE_HIGH));  in board_ehci_hcd_init()
99 						    PAD_CTL_DSE_HIGH));  in board_ehci_hcd_init()
115 			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),  in setup_iomux_fec()
116 		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
125 		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
130 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
131 		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
144 		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
147 		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),  in setup_iomux_fec()
166 #define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
169 				 PAD_CTL_DSE_HIGH)
352 #define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
386 			     PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
388 			     PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
390 			     PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
392 			     PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
398 			     PAD_CTL_DSE_HIGH),  in setup_iomux_nand()
400 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
402 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
404 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
406 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
408 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
410 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
412 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
414 			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),  in setup_iomux_nand()
428 					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));  in m53_set_clock()