1 // SPDX-License-Identifier: GPL-2.0+
37 #define EMI1_SLOT5	5
58 static u8 slot_qsgmii_phyaddr[5][4] = {
61 	{4, 5, 6, 7},
111 	struct t4240qds_mdio *priv = bus->priv;  in t4240qds_mdio_read()
113 	t4240qds_mux_mdio(priv->muxval);  in t4240qds_mdio_read()
115 	return priv->realbus->read(priv->realbus, addr, devad, regnum);  in t4240qds_mdio_read()
121 	struct t4240qds_mdio *priv = bus->priv;  in t4240qds_mdio_write()
123 	t4240qds_mux_mdio(priv->muxval);  in t4240qds_mdio_write()
125 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);  in t4240qds_mdio_write()
130 	struct t4240qds_mdio *priv = bus->priv;  in t4240qds_mdio_reset()
132 	return priv->realbus->reset(priv->realbus);  in t4240qds_mdio_reset()
142 		return -1;  in t4240qds_mdio_init()
149 		return -1;  in t4240qds_mdio_init()
152 	bus->read = t4240qds_mdio_read;  in t4240qds_mdio_init()
153 	bus->write = t4240qds_mdio_write;  in t4240qds_mdio_init()
154 	bus->reset = t4240qds_mdio_reset;  in t4240qds_mdio_init()
155 	strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));  in t4240qds_mdio_init()
157 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);  in t4240qds_mdio_init()
159 	if (!pmdio->realbus) {  in t4240qds_mdio_init()
163 		return -1;  in t4240qds_mdio_init()
166 	pmdio->muxval = muxval;  in t4240qds_mdio_init()
167 	bus->priv = pmdio;  in t4240qds_mdio_init()
177 	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;  in board_ft_fman_fixup_port()
278 		char lane_mode[20] = {"10GBASE-KR"};  in board_ft_fman_fixup_port()
279 		char buf[32] = "serdes-2,";  in board_ft_fman_fixup_port()
288 				sprintf(buf, "%s%s%s", buf, "lane-a,",  in board_ft_fman_fixup_port()
297 				sprintf(buf, "%s%s%s", buf, "lane-b,",  in board_ft_fman_fixup_port()
306 				sprintf(buf, "%s%s%s", buf, "lane-d,",  in board_ft_fman_fixup_port()
315 				sprintf(buf, "%s%s%s", buf, "lane-c,",  in board_ft_fman_fixup_port()
324 			/* fixed-link is used for XFI fiber cable */  in board_ft_fman_fixup_port()
325 			fdt_delprop(blob, offset, "phy-handle");  in board_ft_fman_fixup_port()
331 			fdt_setprop(blob, offset, "fixed-link", &f_link,  in board_ft_fman_fixup_port()
336 					"fsl,fman-memac-mdio", pa + 0x1000);  in board_ft_fman_fixup_port()
337 			fdt_setprop_string(blob, off, "lane-instance", buf);  in board_ft_fman_fixup_port()
346 	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;  in fdt_fixup_board_enet()
495 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &  in board_eth_init()
498 	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &  in board_eth_init()
521 	/* Register the muxing front-ends to the MDIO buses */  in board_eth_init()
599 		idx = i - FM1_DTSEC1;  in board_eth_init()
625 			if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()
656 		idx = i - FM1_10GEC1;  in board_eth_init()
660 				/* A fake PHY address to make U-Boot happy */  in board_eth_init()
668 				if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()
777 		idx = i - FM2_DTSEC1;  in board_eth_init()
803 			if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()
821 			 * the first on-board RGMII port.  If DTSEC6 is RGMII,  in board_eth_init()
822 			 * then it's routed via via EC2 to the second on-board  in board_eth_init()
837 		idx = i - FM2_10GEC1;  in board_eth_init()
841 				/* A fake PHY address to make U-Boot happy */  in board_eth_init()
849 				if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()