Lines Matching +full:zero +full:- +full:initialised

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  *  Cache-handling routined for MIPS CPUs
8 #include <asm-offsets.h>
51 	srl	\line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
53 	move	\sz, zero
59 	srl	\sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
67 	srl	$1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
83  * mips_cache_reset - low level initialisation of the primary caches
91  * memory starting at location zero to be used as a source of parity.
94  * may clobber typically callee-saved registers.
116 	move	R_L2_SIZE, zero
117 	move	R_L2_LINE, zero
118 	move	R_L2_BYPASSED, zero
119 	move	R_L2_L2C, zero
171 	/* Zero the L2 tag registers */
172 	sw	zero, GCR_L2_TAG_ADDR(t0)
173 	sw	zero, GCR_L2_TAG_ADDR_UPPER(t0)
174 	sw	zero, GCR_L2_TAG_STATE(t0)
175 	sw	zero, GCR_L2_TAG_STATE_UPPER(t0)
176 	sw	zero, GCR_L2_DATA(t0)
177 	sw	zero, GCR_L2_DATA_UPPER(t0)
186 	 * For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
216 	/* Zero the L2 tag registers */
217 	mtc0	zero, CP0_TAGLO, 4
251 	 * Now clear that much memory starting from zero.
256 	f_fill64	a0, -64, zero
276 	 * If the L2 was bypassed then we already initialised the L1s before
288 	mtc0		zero, CP0_TAGLO
289 	mtc0		zero, CP0_TAGLO, 2
302 	 * Initialize the I-cache first,
313 	/* invalidate again - prudent but not strictly neccessary */
320 	 * Enable use of the I-cache by setting Config.K0. The code for this
334 	 * then initialize D-cache.
344 2:	LONG_L		zero, 0(t0)
357 	/* The L2 is bypassed - go initialise it */