Lines Matching full:t1
147 lw t1, GCR_L2_CONFIG(t0)
148 bgez t1, l2_probe_done
150 ext R_L2_LINE, t1, \
156 ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
160 ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
166 or t1, t1, GCR_L2_CONFIG_BYPASS
167 sw t1, GCR_L2_CONFIG(t0)
195 li t1, 2
196 sllv R_L2_LINE, t1, R_L2_LINE
198 srl t1, t0, MIPS_CONF2_SA_SHF
199 andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
200 addiu t1, t1, 1
201 mul R_L2_SIZE, R_L2_LINE, t1
203 srl t1, t0, MIPS_CONF2_SS_SHF
204 andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
205 sllv R_L2_SIZE, R_L2_SIZE, t1
206 li t1, 64
207 mul R_L2_SIZE, R_L2_SIZE, t1
247 sltu t1, R_IC_SIZE, R_DC_SIZE
248 movn v0, R_DC_SIZE, t1
270 PTR_ADDU t1, t0, R_L2_SIZE
273 bne t0, t1, 1b
306 PTR_ADDU t1, t0, R_IC_SIZE
308 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
312 cache_loop t0, t1, R_IC_LINE, FILL
315 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
326 li t1, CPHYSADDR(~0)
327 and t0, t0, t1
328 PTR_LI t1, CKSEG1
329 or t0, t0, t1
338 PTR_ADDU t1, t0, R_DC_SIZE
340 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
346 bne t0, t1, 2b
349 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
365 lw t1, GCR_L2_CONFIG(t0)
366 xor t1, t1, GCR_L2_CONFIG_BYPASS
367 sw t1, GCR_L2_CONFIG(t0)
400 lw t1, GCR_REV(t0)
403 bge t1, t2, 1f