Lines Matching refs:clrbits_le32
33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
371 clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
372 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
373 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
374 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
377 clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN); in mctl_sys_init()
380 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
433 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
469 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
480 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
566 clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); in mctl_channel_init()
755 clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); in sunxi_dram_init()